SEMICONDUCTOR DEVICE INCLUDING TEST STRUCTURE

• US 20190326187A1
• Filed: 11/15/2018
• Published: 10/24/2019
• Est. Priority Date: 04/20/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: SAGONG, Hyun Chul, PARK, June Kyun, KIM, Hyun Jin, CHOI, Ki Hyun, PAE, Sang Woo
• Granted Patent: US 11,488,877 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor device including a test structure includes a semiconductor substrate and a plurality of test structures on the semiconductor substrate. The test structures include respective lower active regions extending from the semiconductor substrate in a vertical direction and having different widths, and upper active regions extending from respective lower active regions in the vertical direction. Each of the lower active regions includes first regions and second regions. The first regions overlap the upper active regions and are between the second regions, and the second regions include outer regions and inner regions between the outer regions. The outer regions, located in the lower active regions having different widths, have different widths.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate; and

a plurality of test structures on the semiconductor substrate,

wherein the test structures comprise respective lower active regions protruding from the semiconductor substrate in a vertical direction and having different widths, and upper active regions protruding from the respective lower active regions in the vertical direction,

wherein the respective lower active regions comprise first regions and second regions,

wherein the first regions overlap the upper active regions and are between the second regions,

wherein the second regions comprise outer regions, and inner regions between the outer regions, and

wherein the outer regions of the respective lower active regions have different widths.

2. The semiconductor device of claim 1, wherein the inner regions of the respective lower active regions have a same width.

3. The semiconductor device of claim 1, wherein one of the outer regions of one lower active region of the respective lower active regions has an upper surface defining a first angle with a side surface thereof,

wherein one of the outer regions of another lower active region of the respective lower active regions has an upper surface defining a second angle with a side surface thereof, and

wherein the first angle is different from the second angle.

4. The semiconductor device of claim 1, wherein one of the outer regions of one lower active region of the respective lower active regions has an upper surface defining an acute angle with a side surface thereof, and

wherein one of the outer regions of another lower active region of the respective lower active regions has an upper surface defining an obtuse angle with a side surface thereof.

5. The semiconductor device of claim 1, wherein each of the inner regions has a width that is greater than a width of each of the outer regions.

6. The semiconductor device of claim 1, wherein the test structures further include gate structures and source/drain regions,

wherein the gate structures overlap the respective lower active regions and the upper active regions protruding therefrom, and

wherein the source/drain regions are on the upper active regions, and are between the gate structures in plan view.

7. The semiconductor device of claim 6, wherein the source/drain regions comprise an epitaxial semiconductor layer extending from recess regions of the upper active regions.

8. The semiconductor device of claim 6, further comprising:

first isolation regions on the second regions of the lower active regions; and

a second isolation region extending in the vertical direction along side surfaces of the lower active regions, and adjacent the upper active regions and the first isolation regions.

9. The semiconductor device of claim 8, wherein the upper active regions protrude in the vertical direction between the first isolation regions, and

wherein the gate structures extend on upper surfaces and side surfaces of the upper active regions.

10. A semiconductor device, comprising:

a semiconductor substrate; and

a plurality of test structures on the semiconductor substrate,

wherein the plurality of test structures comprise;

lower active regions protruding from the semiconductor substrate in a vertical direction that is perpendicular to the semiconductor substrate, the lower active regions having different widths;

upper active regions protruding from each of the lower active regions in the vertical direction, the upper active regions extending in a first horizontal direction; and

gate structures extending in a second horizontal direction that is perpendicular to the first horizontal direction, the gate structures having portions overlapping the lower active regions and the upper active regions,

wherein each of the lower active regions comprises first regions overlapping the upper active regions, and second regions not overlapping the upper active regions, and

wherein the second regions comprise outer regions, and inner regions between the outer regions.

11. The semiconductor device of claim 10, further comprising a plurality of circuit structures on the semiconductor substrate,

wherein the circuit structures include a circuit lower active region extending from the semiconductor substrate in the vertical direction, circuit upper active regions on the circuit lower active region, and a circuit gate structure comprising portions that overlap the circuit lower active region and the circuit upper active regions, and

wherein the circuit lower active region comprises an outer region having a width equal to a width of one outer region among the outer regions of the plurality of test structures, and

wherein a variance between the different widths of the lower active regions of the plurality of test structures is greater than a variance between widths of respective circuit lower active regions of the plurality of circuit structures.

12. The semiconductor device of claim 10, wherein one of the outer regions of one lower active region of the lower active regions has an upper surface defining an acute angle with a side surface thereof.

13. The semiconductor device of claim 10, wherein:

the inner regions, of the lower active regions having the different widths, have respective first widths that are equal to each other; and

the outer regions, of the lower active regions having the different widths, have respective widths that are different from each other and are less than the respective first widths.

14. The semiconductor device of claim 10, wherein the outer regions, of at least two of the lower active regions having the different widths, have respective ends with different heights.

15. The semiconductor device of claim 10, further comprising a gate connection portion,

wherein the plurality of test structures comprise a first test structure,

wherein the first test structure comprises a first lower active region, first upper active regions extending from the first lower active region in the vertical direction, and first gate structures comprising portions overlapping the first lower active region and the first upper active regions, and

wherein the gate connection portion electrically connects the first gate structures.

16. A semiconductor device, comprising:

a memory cell array region comprising a unit memory cell region; and

a test region comprising a unit test region having a planar area equal to a planar area of the unit memory cell region,

wherein the unit memory cell region comprises;

a pair of first memory active lines adjacent to each other and intersecting the unit memory cell region;

a pair of second memory active lines adjacent to each other and intersecting the unit memory cell region;

a single third memory active line between the pair of first memory active lines and the pair of second memory active lines; and

a single fourth memory active line between the pair of first memory active lines and the pair of second memory active lines,

and wherein the unit test region comprises;

a pair of first test active lines adjacent to each other and intersecting the unit test region;

a pair of second test active lines adjacent to each other and intersecting the unit test region;

a single third test active line adjacent to the pair of first test active lines; and

a single fourth test active line adjacent to the pair of second test active lines,

wherein each of the third and fourth memory active lines has an end portion in the unit memory cell region, and

wherein each of the third and fourth test active lines intersects the unit test region and is free of an end portion therein.

17. The semiconductor device of claim 16, further comprising:

a first memory gate structure intersecting the pair of first memory active lines and the third memory active line;

a second memory gate structure intersecting the pair of second memory active lines and the fourth memory active line;

a third memory gate structure having an end portion opposing an end portion of the second memory gate structure, and intersecting the pair of first memory active lines; and

a fourth memory gate structure having an end portion opposing an end portion of the first memory gate structure, and intersecting the pair of second memory active lines.

18. The semiconductor device of claim 16, further comprising:

memory source/drain regions, comprising;

a first memory source/drain region, a second memory source/drain region, and a third memory source/drain region, on the pair of first memory active lines and being spaced apart from each other;

a fourth memory source/drain region, a fifth memory source/drain region, and a sixth memory source/drain region, on the pair of second memory active lines and being spaced apart from each other;

a seventh memory source/drain region and an eighth memory source/drain region, on the third memory active line and being spaced apart from each other; and

a ninth memory source/drain region and a tenth memory source/drain region, on the fourth memory active line and being spaced apart from each other; and

test source/drain regions, comprising;

a first test source/drain region, a second test source/drain region, and a third test source/drain region, on the pair of first test active lines and being spaced apart from each other;

a fourth test source/drain region, a fifth test source/drain region, and a sixth test source/drain region, on the pair of second test active lines and being spaced apart from each other;

a seventh test source/drain region and an eighth test source/drain region on the third test active line and being spaced apart from each other; and

a ninth test source/drain region and a tenth test source/drain region on the fourth test active line and being spaced apart from each other,

wherein each of the first, second, and third memory source/drain regions comprises an epitaxial layer, extending from each of the pair of first memory active lines,

wherein each of the fourth, fifth, and sixth memory source/drain regions comprises an epitaxial layer, extending from each of the pair of second memory active lines,

wherein each of the first, second, and third test source/drain regions comprises an epitaxial layer, extending from each of the pair of first test active lines, and

wherein each of the fourth, fifth, and sixth test source/drain regions comprises an epitaxial layer, extending from each of the pair of second test active lines.

19. The semiconductor device of claim 18, wherein the test source/drain regions further comprise:

an eleventh test source/drain region on the fourth test active line; and

a twelfth test source/drain region on the third test active line,

wherein the first to sixth memory source/drain regions, and the first to sixth test source/drain regions, have N-type conductivity, and

the seventh to tenth memory source/drain regions, and the seventh to twelfth test source/drain regions, have P-type conductivity.

20. The semiconductor device of claim 19, wherein a quantity of the test source/drain regions that oppose each other and have different conductivity types in the unit test region is greater than a quantity of the memory source/drain regions that oppose each other and have different conductivity types in the unit memory cell region.