Packaged Integrated Circuit With Interposing Functionality and Method for Manufacturing Such a Packaged Integrated Circuit

• US 20190326188A1
• Filed: 03/21/2019
• Published: 10/24/2019
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: AT&S Austria Technologie & Systemtechnik AG
• Original Assignee: AT&S Austria Technologie & Systemtechnik AG
• Inventors: Tuominen, Mikael, Vockenberger, Christian
• Granted Patent: US 11,605,569 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/80856 Pre-cured adhesive, i.e. B-stage adhesive
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/142 : HF devices
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4655 : by using a laminate characterized by the insulating layer general-purpose insulating materials H05K1/03, H05K3/4673
• CPC Class Codes: H05K 3/4697 : having cavities, e.g. for mounting components H05K3/4691 takes precedence

Abstract

A packaged integrated circuit includes a core structure with a cavity therein; a component accommodated in the cavity; an electrically insulating structure formed over the core structure and the component; a partially electrically insulating carrier structure formed below the core structure and the component; and an electrically conducting redistribution arrangement formed at least partially within the carrier structure. The redistribution arrangement includes conductor structures each having a first element extending through the carrier structure and electrically connecting a contact of the component and a second element below the carrier structure. A part of the second element is a contact pad for electrically connecting the redistribution arrangement with external circuitry. The carrier structure includes a polyimide layer and an adhesive layer. The adhesive layer is directly attached to an upper surface of the polyimide layer and to a lower surface of the core structure and a lower surface of the component.

Claims

1. A packaged integrated circuit, comprising:

a core structure having a through passage cavity formed therein;

an integrated circuit component being accommodated within the cavity;

an electrically insulating cover structure formed over the core structure and the component;

an at least partially electrically insulating carrier structure formed below the core structure and the component; and

an electrically conducting redistribution arrangement formed at least partially within the carrier structure;

wherein the redistribution arrangement comprises at least two conductor structures each having

a first conductor element extending through the carrier structure and electrically contacting one contact element of the component and a second conductor element being formed below the carrier structure,

wherein at least a part of the second conductor element is configured for electrically contacting the redistribution arrangement with external circuitry,

wherein a first spacing between the two contact elements is smaller than a second spacing between the two second conductor elements; and

wherein the carrier structure comprises at least a polyimide layer and an adhesive layer,

wherein the adhesive layer is directly attached to an upper surface of the polyimide layer and to a lower surface of the core structure and a lower surface of the component.

2. The packaged integrated circuit as set forth in claim 1, wherein the second conductor element is directly attached to the polyimide layer.

3. The packaged integrated circuit as set forth claim 1, wherein the cover structure is a laminated cover structure.

4. The packaged integrated circuit as set forth in claim 3, wherein the cover structure fills at least one side gap being present between a side surface of the component and a side wall of the cavity.

5. The packaged integrated circuit as set forth in claim 3, wherein the laminated cover structure is made from a single laminating sheet which includes an electrically insulating layer and at least one electrically conductive layer formed at a surface of the electrically insulating layer.

6. The packaged integrated circuit as set forth in claim 1, wherein each conductor structure further has a third conductor element being formed between the adhesive layer and the component, wherein at least a part of the third conductor element is a further contact pad for electrically contacting the component with the redistribution arrangement.

7. The packaged integrated circuit as set forth in claim 1, wherein the first conductor element is a metallized via.

8. The packaged integrated circuit as set forth in claim 1, wherein the core structure comprises a cured first PCB material selected from the group consisting of resin, reinforced or non-reinforced resin, epoxy resin or Bismaleimide-Triazine resin, FR-4, FR-5, cyanate ester, polyphenylene derivate, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based Build-Up Film, polytetrafluoroethylene, a ceramic, and a metal oxide.

9. The packaged integrated circuit as set forth in claim 1, wherein the cover structure is made from a second PCB material selected from the group consisting of a prepreg material, a resin, a resin sheet, a cyanate ester, a polyphenylene derivate, a liquid crystal polymer, a resin-based Build-Up Film, an epoxy-based Build-Up Film.

10. The packaged integrated circuit as set forth in claim 1, wherein at least one of the redistribution arrangement and the at least one electrically conducting layer comprise a material being selected from the group consisting of copper, aluminum, nickel, silver, gold, palladium, and tungsten, any of the mentioned materials being optionally coated with a supra-conductive material.

11. The packaged integrated circuit as set forth in claim 1, wherein the component is selected from a group consisting of an active electronic component, an electronic chip, a storage device, a filter, a signal processing component, a power management component, an optoelectronic interface element, a voltage converter, a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, a microprocessor, and a logic chip.

12. A method for manufacturing an integrated circuit package as set forth in claim 1, the method comprising:

providing a core structure having a through passage cavity formed therein;

placing an integrated circuit component in the cavity;

providing an at least partially electrically insulating carrier structure and an electrically conducting redistribution arrangement below the core structure or the component; and

forming an electrically insulating cover structure over the core structure and the component.

13. The method as set forth in claim 12, wherein, before placing the component in the cavity, the at least partially electrically insulating carrier structure is formed at a lower surface of the core structure such that, when placing the component in the cavity, the component is directly attached to an adhesive layer.

14. The method as set forth in claim 12, further comprising:

before placing the component within the cavity, forming a temporary carrier structure at a lower surface of the core structure such that, when placing the component within the cavity, the component is directly attached to the temporary carrier structure;

after forming the cover structure over the core structure and the component, removing the temporary carrier structure from the core structure or the component, respectively, and

forming a carrier structure below the core structure and the component.

15. The method as set forth in claim 14, wherein,

after the carrier structure has been formed below the core structure and the component,

forming the redistribution arrangement at least partially within the carrier structure.