EMBEDDED BRIDGE WITH THROUGH-SILICON VIAS

• US 20190326198A1
• Filed: 06/28/2019
• Published: 10/24/2019
• Est. Priority Date: 06/30/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Vaidya, Aditya S., Mahajan, Ravindranath V., Raorane, Digvijay A., Start, Paul R.
• Granted Patent: US 11,049,798 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias

Abstract

An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Claims

1. An integrated circuit (IC) package, comprising:

a-substrate, and

a bridge die within the substrate, the bridge die comprising a plurality of vias extending from a first side to a second side of the-bridge die, wherein the bridge die comprises a first plurality of pads on the first side and a second plurality of pads on the second side, wherein the plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads, and wherein the bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

2. The IC package of claim 1, wherein at least a portion of the second plurality of pads on the second side of the bridge die is electrically coupled to a trace routing in the substrate.

3. The IC package of claim 1, wherein at least a portion of the first plurality of pads on the first side of the bridge die is electrically coupled to pads on a surface of the substrate.

4. The IC package of claim 1, wherein sidewalls of the ones of the second plurality of pads are adjacent to the layer of silicon oxide, and wherein tops of the ones of the second plurality of pads are planar with the layer of silicon oxide and are within openings in the adhesive film.

5. The IC package of claim 1, wherein the adhesive film is over the ones of the second plurality of pads.

6. The IC package of claim 5, wherein the adhesive film comprises conductive particles.

7. The IC package of claim 1, wherein the adhesive film is a die backside film.

8. The IC package of claim 1, wherein the adhesive film is an epoxy flux film.

9. The IC package of claim 1, wherein the adhesive film is an epoxy flux paste.

10. The IC package of claim 1, wherein the adhesive film is a wafer-level under film.

11. The IC package of claim 1, wherein the adhesive film surrounds solder joints between the ones of the second plurality of pads.

12. The IC package of claim 1, wherein the bridge die is within a cavity in the substrate.

13. The IC package of claim 12, wherein the adhesive film is adhesively bonded to a wall of the cavity.

14. The IC package of claim 1, wherein the adhesive film is electrically conducive and wherein the adhesive film couples the second plurality of pads to a conductive layer within the substrate.

15. The IC package of claim 1, wherein the first plurality of pads is electrically coupled to a conductive layer on a surface of the substrate.

16. The IC package of claim 1, wherein the-bridge die comprises silicon.

17. A system comprising:

a first active die coupled to a substrate; and

a second active die coupled to the substrate, wherein;

the substrate comprises a bridge die within a cavity, the bridge die comprising a plurality of vias extending from a first side to a second side of the bridge die, wherein the bridge die comprises a first plurality of pads on the first side and a second plurality of pads on the second side, wherein the plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads, and wherein the bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die,

wherein ones of the first plurality of pads are coupled to a first signal routing on the first active die and to a second signal routing on the second active die.

18. The system of claim 17, wherein the first signal routing is coupled to the second signal routing by traces on the first side of the bridge die extending between ones of the first plurality of pads.

19. The system of claim 17, wherein the second plurality of pads is coupled to power routing traces in the substrate.

20. The system of claim 19, wherein an adhesive conductive film couples the second plurality of pads to the power routing traces in the substrate.