SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME

• US 20190326202A1
• Filed: 07/02/2019
• Published: 10/24/2019
• Est. Priority Date: 03/15/2013
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: ARBUTHNOT, Roger M., ST. GERMAIN, Stephen
• Application Number:
  US16/459,954
• Publication Number:
  US 20190326202A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04034 Bonding areas specifically adapted for strap connectors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/32258 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/37011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/37012 Cross-sectional shape
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/40499 : Material of the auxiliary connecting means
• CPC Class Codes: H01L 2224/4103 : Connectors having different sizes
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73221 : Strap and wire connectors
• CPC Class Codes: H01L 2224/73263 : Layer and strap connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83815 : Reflow soldering
• CPC Class Codes: H01L 2224/84385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/84801 : Soldering or alloying
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/492 : Bases or plates or solder therefor
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/41 : of a plurality of strap connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/67 : of a plurality of connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Various leadframe implementations may include a conductive substrate electrically coupled to a first lead where the conductive substrate includes a first elevated region and a second elevated region on a first side of the conductive substrate. The first elevated region may include a first planar surface and the second elevated region may include a second planar surface on the first side of the conductive substrate. Various implementations may include where the first planar surface of the first elevated region and the second planar surface of the second elevated region are configured to attach to a contact pad of a semiconductor die. The first planar surface may include a curved edge. The second planar surface may include a polygonal shape. The curved edge of the first planar surface may be configured to laterally align with a curved edge of the contact pad of the semiconductor die.

Claims

1. A leadframe comprising:

a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region on a first side of the conductive substrate and a second elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate;

wherein the first planar surface of the first elevated region and the second planar surface of the second elevated region are configured to attach to a contact pad of a semiconductor die;

wherein the first planar surface comprises a curved edge;

wherein the second planar surface has a polygonal shape; and

wherein the curved edge of the first planar surface is configured to laterally align with a curved edge of the contact pad of the semiconductor die.

2. The leadframe of claim 1, wherein the conductive substrate comprises at least 10 elevated regions.

3. The leadframe of claim 1, wherein the conductive substrate is at least partially encapsulated in a molding material.

4. The leadframe of claim 1, wherein the second planar surface of the second elevated region has a first corner that is laterally aligned with a first corner of the contact pad.

5. The leadframe of claim 1, wherein the conductive substrate further comprises a third elevated region on the first side of the conductive substrate;

wherein the third elevated comprises a third planar surface on the first side of the conductive substrate; and

wherein the third planar surface of the third elevated region is configured to attach to the contact pad of the semiconductor die.

6. The leadframe of claim 5, wherein the third planar surface has a polygonal shape with different dimensions than the polygonal shape of the second planar surface.

7. The leadframe of claim 1, wherein the first planar surface of the first elevated region is rectangular.

8. The leadframe of claim 1, wherein the conductive substrate comprises at least six elevated regions on the first side of the conductive;

and

wherein each of the at least six elevated regions comprise a planar surface that is configured to attach to the contact pad of the semiconductor die.

9. A leadframe comprising:

a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region on a first side of the conductive substrate and a second elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate;

wherein the first planar surface of the first elevated region and the second planar surface of the second elevated region are both configured to be soldered to a contact pad of a semiconductor die; and

wherein only a portion of the first planar surface is configured to be soldered to the contact pad of the semiconductor die.

10. The leadframe of claim 9, wherein the conductive substrate comprises at least 10 elevated regions.

11. The leadframe of claim 9, wherein the second planar surface of the second elevated region has a first corner that is laterally aligned with a first corner of the contact pad.

12. The leadframe of claim 9, wherein the conductive substrate further comprises a third elevated region on the first side of the conductive substrate;

wherein the third elevated comprises a third planar surface on the first side of the conductive substrate; and

wherein the third planar surface of the third elevated region is configured to be attached to the contact pad of the semiconductor die.

13. The leadframe of claim 12, wherein the third planar surface has a polygonal shape with different dimensions than the polygonal shape of the second planar surface.

14. The leadframe of claim 9, wherein the first planar surface of the first elevated region is rectangular.

15. The leadframe of claim 9, wherein the conductive substrate comprises at least six elevated regions on the first side of the conductive;

and

wherein each of the at least six elevated regions comprise a planar surface that is configured to attach to the contact pad of the semiconductor die.

16. A leadframe comprising:

a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region on a first side of the conductive substrate and second elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate; and

wherein the conductive substrate is configured to electrically couple to a first contact pad of a semiconductor die and is further configured to solder to both the first planar surface of the first elevated region and the second planar surface of the second elevated region;

wherein the first planar surface of the first elevated region has different dimensions than the second planar surface of the second elevated region; and

wherein the first planar surface of the first elevated region has a first corner that is configured to laterally align with a first corner of the first contact pad.

17. The leadframe of claim 16, wherein the conductive substrate comprises at least 10 elevated regions.

18. The leadframe of claim 16, wherein the conductive substrate further comprises a third elevated region on the first side of the conductive substrate;

wherein the third elevated comprises a third planar surface on the first side of the conductive substrate; and

wherein the third planar surface of the third elevated region is configured to attach to the contact pad.

19. The leadframe of claim 18, wherein the third planar surface has a polygonal shape with different dimensions than the polygonal shape of the second planar surface.

20. The leadframe of claim 16, wherein the conductive substrate comprises at least six elevated regions on the first side of the conductive;

and

wherein each of the at least six elevated regions comprise a planar surface that is configured to attach to the contact pad of the semiconductor die.