MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
First Claim
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1. A method comprising:
- forming a barrier and adhesion layer that connects a modulated copper pillar to a chip;
forming a seed layer contacting the barrier and adhesion layer;
forming a first copper layer contacting the seed layer;
forming a second copper layer contacting a solder material;
forming at least one deformation region having a modulus of elasticity less than copper between the first copper layer and the second copper layer; and
forming protective layers interposed at interfaces between a surface of the at least one deformation region and the first copper layer and the surface of the at least one deformation region and the second copper layer.
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Abstract
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions
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11 Claims
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1. A method comprising:
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forming a barrier and adhesion layer that connects a modulated copper pillar to a chip; forming a seed layer contacting the barrier and adhesion layer; forming a first copper layer contacting the seed layer; forming a second copper layer contacting a solder material; forming at least one deformation region having a modulus of elasticity less than copper between the first copper layer and the second copper layer; and forming protective layers interposed at interfaces between a surface of the at least one deformation region and the first copper layer and the surface of the at least one deformation region and the second copper layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification