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MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME

  • US 20190326242A1
  • Filed: 07/03/2019
  • Published: 10/24/2019
  • Est. Priority Date: 10/11/2007
  • Status: Active Grant
First Claim
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1. A method comprising:

  • forming a barrier and adhesion layer that connects a modulated copper pillar to a chip;

    forming a seed layer contacting the barrier and adhesion layer;

    forming a first copper layer contacting the seed layer;

    forming a second copper layer contacting a solder material;

    forming at least one deformation region having a modulus of elasticity less than copper between the first copper layer and the second copper layer; and

    forming protective layers interposed at interfaces between a surface of the at least one deformation region and the first copper layer and the surface of the at least one deformation region and the second copper layer.

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