Memory Cells and Memory Arrays

• US 20190326292A1
• Filed: 07/02/2019
• Published: 10/24/2019
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mathew, Suraj J., Singanamalla, Raghunath, Ahmed, Fawad, Brown, Kris K., Nair, Vinay, Yang, Gloria, Simsek-Ege, Fatma Arzum, Tran, Diem Thy N.
• Granted Patent: US 10,847,516 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Claims

1. A memory cell comprising:

a three-transistor-one-capacitor (3T-1C) configuration;

the three transistors of the 3T-1C configuration being a first transistor, a second transistor and a third transistor;

a semiconductor pillar extending along the second and third transistors and comprising channel regions and source/drain regions of the second and third transistors;

wherein all of the first, second and third transistors are vertically displaced relative to one another; and

wherein the capacitor of the 3T-1C configuration has an inner node, an outer node, and a dielectric material between the inner and outer nodes;

the inner node being electrically coupled with a source/drain region of the first transistor and with a gate of the second transistor.

2. The memory cell of claim 1 wherein the first transistor is between the capacitor and a bitline.

3. The memory cell of claim 2 wherein the bitline is a write bitline, and wherein a separate read bitline is electrically coupled with a source/drain region of the third transistor.

4. A memory cell comprising:

a three-transistor-one-capacitor (3T-1C) configuration;

the three transistors of the 3T-1C configuration being a first transistor, a second transistor and a third transistor, all of the first, second and third transistors are vertically displaced relative to one another;

a semiconductor pillar extending along the second and third transistors and comprising channel regions and source/drain regions of the second and third transistors;

a read bit line vertically above the first, second and third transistors;

a write bitline vertically below the first second and third transistors, and

a common plate electrically coupled to a node of the capacitor and electrically coupled to a second memory cell capacitor node.

5. The memory cell of claim 4 wherein the capacitor is disposed vertically between the first and second transistors.

6. The memory cell of claim 4 wherein the semiconductor pillar is a first semiconductor pillar, and further comprising a second semiconductor pillar extending along the first transistor.

7. The memory cell of claim 6 wherein a first transistor channel region is disposed within the second semiconductor pillar.

8. The memory cell of claim 6 wherein a first source/drain region of the first transistor is in direct contact with the write bit line.

9. The memory cell of claim 8 wherein a second source/drain region of the first transistor is coupled to a conductive interconnect.

10. The memory cell of claim 9 wherein the conductive interconnect extends between the second conductive pillar and an inner node of the capacitor.

11. A memory cell comprising:

a three-transistor-one-capacitor (3T-1C) configuration;

the three transistors of the 3T-1C configuration being a first transistor, a second transistor and a third transistor, all of the first, second and third transistors are vertically displaced relative to one another;

a first semiconductor pillar extending along the first transistor and comprising a channel region and source/drain regions of the first transistor;

a first conductive interconnect extending between the first pillar and an inner node of the capacitor;

a second semiconductor pillar extending along the second and third transistors and comprising channel regions and source/drain regions of the second and third transistors; and

a second conductive interconnect extending between the second semiconductor pillar and the inner node of the capacitor.

12. The memory cell of claim 11 further comprising:

a read bit line vertically above the first, second and third transistors; and

a write bitline vertically below the first second and third transistors.

13. The memory cell of claim 11 wherein the first and second conductive interconnects comprise metal.

14. The memory cell of claim 11 wherein the inner node comprises metal.

15. The memory cell of claim 11 wherein the inner node, the first conductive interconnect and the second conductive interconnect are formed of a single common material.

16. The memory cell of claim 15 wherein the single common material comprises conductively-doped semiconductor material.

17. The memory cell of claim 15 wherein the single common material comprises one or more metals.

18. The memory cell of claim 15 wherein the second transistor comprises a conductive gate comprising the single common material.