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Memory Cells and Memory Arrays

  • US 20190326292A1
  • Filed: 07/02/2019
  • Published: 10/24/2019
  • Est. Priority Date: 08/31/2016
  • Status: Active Grant
First Claim
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1. A memory cell comprising:

  • a three-transistor-one-capacitor (3T-1C) configuration;

    the three transistors of the 3T-1C configuration being a first transistor, a second transistor and a third transistor;

    a semiconductor pillar extending along the second and third transistors and comprising channel regions and source/drain regions of the second and third transistors;

    wherein all of the first, second and third transistors are vertically displaced relative to one another; and

    wherein the capacitor of the 3T-1C configuration has an inner node, an outer node, and a dielectric material between the inner and outer nodes;

    the inner node being electrically coupled with a source/drain region of the first transistor and with a gate of the second transistor.

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