MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

• US 20190326304A1
• Filed: 02/27/2019
• Published: 10/24/2019
• Est. Priority Date: 04/18/2018
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Chen, Yen-Ting, Lo, Ming-Shan
• Granted Patent: US 10,692,981 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: H01L 21/02107 Forming insulating materials on a substrate
• CPC Class Codes: H01L 21/02109 characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02225 characterised by the process for the formation of the insulating layer
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/0226 formation by a deposition process per se C23C
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Abstract

A memory device and a manufacturing method thereof are provided. The memory device includes a first gate structure, a second gate structure, an oxide layer and a nitride layer. The first gate structure and the second gate structure are disposed on a substrate. The oxide layer covers the first gate structure. The nitride layer is disposed on the substrate and covers the oxide and the second gate structure. The refraction index of a portion of the nitride layer adjacent to an interface between the nitride layer and each of the first gate structure and the second gate structure is about 5% to 10% less than the refraction index of the remaining portion of the nitride layer.

Claims

1. A memory device, comprising:

a first gate structure and a second gate structure, disposed on a substrate;

an oxide layer, covering the first gate structure; and

a nitride layer, disposed on the substrate and covering the oxide layer and the second gate structure,

wherein a refraction index of a portion of the nitride layer adjacent to an interface between the nitride layer and each of the first gate structure and the second gate structure is about 5% to 10% less than a refraction index of a remaining portion of the nitride layer.

2. The memory device of claim 1, wherein the first gate structure is a floating gate structure, and the second gate structure is a select gate structure.

3. The memory device of claim 1, wherein a thickness of the portion of the nitride layer adjacent to the interface between the nitride layer and each of the first gate structure and the second gate structure is about 1% to 10% of a thickness of the nitride layer.

4. A memory device, comprising:

a first gate structure and a second gate structure, disposed on a substrate;

an oxide layer, covering the first gate structure;

a first nitride layer, disposed on the substrate and covering the oxide layer and the second gate structure; and

a second nitride layer, disposed on the first nitride layer,

wherein a refraction index of the first nitride layer is about 5% to 10% less than a refraction index of the second nitride layer.

5. The memory device of claim 4, wherein the first gate structure is a floating gate structure, and the second gate structure is a select gate structure.

6. The memory device of claim 4, wherein a thickness of the first nitride layer is about 1% to 10% of a total thickness of the first nitride layer and the second nitride layer.

7. A manufacturing method of a memory device, comprising:

forming a first gate structure and a second gate structure on a substrate;

forming an oxide layer on a surface of the first gate structure; and

performing a chemical vapor deposition process to form a nitride layer on the substrate, the nitride layer covering the oxide layer and the second gate structure,

wherein in the chemical vapor deposition process, a RF power supply increases a power from zero to a predetermined final power, such that a refraction index of a portion of the nitride layer adjacent to an interface between the nitride layer and each of the first gate structure and the second gate structure is about 5% to 10% less than a refraction index of a remaining portion of the nitride layer.

8. The manufacturing method of claim 7, wherein the first gate structure is a floating gate structure, and the second gate structure is a select gate structure.

9. The manufacturing method of claim 7, wherein a thickness of the portion of the nitride layer adjacent to the interface between the nitride layer and each of the first gate structure and the second gate structure is about 1% to 10% of a thickness of the nitride layer.

10. The manufacturing method of claim 9, wherein a method of forming the oxide layer comprises:

forming an oxide material layer conformally on the substrate; and

performing a patterning process to remove a portion of the oxide material layer, leaving the oxide material layer on a surface of the first gate structure.

11. The manufacturing method of claim 7, wherein the predetermined final power is between about 300 W and 500 W.

12. The manufacturing method of claim 11, wherein the RF power supply increases the power from zero to the predetermined final power at a rate of about 3,000 W/sec to 10,000 W/sec.

13. The manufacturing method of claim 7, wherein the RF power supply increases the power from zero to the predetermined final power in a period of about 0.01 second to 1 second.