VERTICAL-TYPE MEMORY DEVICE

• US 20190326318A1
• Filed: 01/08/2019
• Published: 10/24/2019
• Est. Priority Date: 04/20/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JUNG, Kwang Young, KIM, Dong Won
• Granted Patent: US 10,950,620 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A vertical-type memory device a vertical-type memory device comprising a substrate including a first region and a second region, adjacent to the first region, a first conductive layer extending on the first region and the second region, and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.

Claims

1. A vertical-type memory device comprising:

a substrate including a first region and a second region, adjacent to the first region;

a first conductive layer extending on the first region and the second region; and

a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer,

wherein an upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.

2. The vertical-type memory device of claim 1, wherein the first conductive layer has a bent portion along the step portion.

3. The vertical-type memory device of claim 2, wherein a first interval between a lower surface of the second conductive layer in the first region and an upper surface of the first conductive layer in the first region is greater than a second interval between the lower surface of the second conductive layer in the second region and the upper surface of the first conductive layer in the second region.

4. The vertical-type memory device of claim 3, wherein a difference between the first interval and the second interval is the same as a height of the step portion.

5. The vertical-type memory device of claim 1, wherein a first interval between a lower surface of the first conductive layer in the first region and the upper surface of the substrate in the first region is greater than a second interval between the lower surface of the first conductive layer in the second region and the upper surface of the substrate in the second region.

6. The vertical-type memory device of claim 5, wherein a difference between the first interval and the second interval is the same as a height of the step portion.

7. The vertical-type memory device of claim 1, further comprising:

a separation pattern on the first region and the second region of the substrate, the separation pattern dividing the first conductive layer and the second conductive layer,

wherein a lower surface of the separation pattern has a step portion at the boundary between the first region and the second region.

8. The vertical-type memory device of claim 1, further comprising:

at least one channel structure in the first region, and passing through the first conductive layer and the second conductive layer; and

at least one dummy channel structure in the second region, and passing through at least one of the first conductive layer and the second conductive layer,

wherein a vertical length of the at least one channel structure is greater than a vertical length of the at least one dummy channel structure.

9. The vertical-type memory device of claim 8, wherein the at least one dummy channel structure has a horizontal cross-sectional area greater than a horizontal cross-sectional area of the at least one channel structure.

10. The vertical-type memory device of claim 8, wherein each of the at least one channel structure and the at least one dummy channel structure includes,

a channel layer extending perpendicularly to the upper surface of the substrate, and

an epitaxial layer between the channel layer and the substrate, and

a height of an upper surface of the epitaxial layer in the first region is different from a height of an upper surface of the epitaxial layer in the second region.

11. The vertical-type memory device of claim 1, further comprising:

a high voltage transistor in a third region of the substrate, the high voltage transistor including a high voltage gate insulating layer, the third region of the substrate adjacent to the second region of the substrate; and

a low voltage transistor in the third region of the substrate, the low voltage transistor including a low voltage gate insulating layer, a thickness of the low voltage gate insulating layer less than a thickness of the high voltage gate insulating layer,

wherein a height of the step portion at the boundary between the first region and the second region is the same as a thickness of the high voltage gate insulating layer.

12. A vertical-type memory device comprising:

a substrate including a cell array region and a connection region adjacent to the cell array region;

a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region;

a plurality of channel structures in the cell array region, the plurality of channel structures passing through the plurality of gate electrode layers; and

a plurality of dummy channel structures in the connection region, the plurality of dummy channel structures passing through at least one of the plurality of gate electrode layers,

wherein an upper surface of the substrate has a step portion at a boundary between the cell array region and the connection region, and

a vertical length of the plurality of channel structures is greater than a vertical length of the plurality of dummy channel structures.

13. The vertical-type memory device of claim 12, further comprising:

a first gate electrode layer adjacent to the substrate among the plurality of gate electrode layers; and

a buffer insulating layer between the first gate electrode layer and the substrate,

wherein a thickness of the buffer insulating layer in the cell array region is greater than a thickness of the buffer insulating layer in the connection region.

14. The vertical-type memory device of claim 12, further comprising:

an interlayer insulating layer between a first gate electrode layer adjacent to the substrate and a second gate electrode layer adjacent to the first gate electrode layer, the first gate electrode layer and the second gate electrode layer from among the plurality of gate electrode layers,

wherein a thickness of the interlayer insulating layer in the cell array region is greater than a thickness of the interlayer insulating layer in the connection region.

15. The vertical-type memory device of claim 12, wherein

the plurality of gate electrode layers comprise a first gate electrode layer adjacent to the substrate, and a second gate electrode layer adjacent to the first gate electrode layer;

the first gate electrode layer comprises a bent portion bent along the upper surface of the substrate; and

a first interval between a lower surface of the second gate electrode layer in the cell array region and an upper surface of the first gate electrode layer in the cell array region is greater than a second interval between the lower surface of the second gate electrode layer in the cell array region and the upper surface of the first gate electrode layer in the connection region.

16. The vertical-type memory device of claim 15, wherein a difference between the first interval and the second interval is the same as a height of the step portion.

17. A vertical-type memory device comprising:

a substrate including a cell array region and a connection region adjacent to the cell array region;

a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region;

a plurality of channel structures in the cell array region, and passing through the plurality of gate electrode layers; and

a plurality of dummy channel structures in the connection region, and passing through at least one of the plurality of gate electrode layers,

wherein an upper surface of the substrate has a step portion at a boundary between the cell array region and the connection region, and

each of the plurality of channel structures includes a first epitaxial layer in contact with the substrate, each of the plurality of dummy channel structures includes a second epitaxial layer in contact with the substrate, and a height of an upper surface of the first epitaxial layer is different from a height of an upper surface of the second epitaxial layer.

18. The vertical-type memory device of claim 17, wherein the height of the upper surface of the first epitaxial layer is lower than the height of the upper surface of the second epitaxial layer.

19. The vertical-type memory device of claim 17, wherein the upper surface of the substrate has a step portion at a boundary between the cell array region and the connection region, and a vertical length of the plurality of channel structures is greater than a vertical length of the plurality of dummy channel structures.

20. The vertical-type memory device of claim 17, wherein the plurality of gate electrode layers comprise a first gate electrode layer adjacent to the substrate, and a second gate electrode layer adjacent to the first gate electrode layer;

the first gate electrode layer comprises a bent portion bent along the upper surface of the substrate; and

a first interval between a lower surface of the second gate electrode layer and an upper surface of the first gate electrode layer in the cell array region is greater than a second interval between the lower surface of the second gate electrode layer and the upper surface of the first gate electrode layer in the connection region.