VERTICAL-TYPE MEMORY DEVICE
First Claim
Patent Images
1. A vertical-type memory device comprising:
- a substrate including a first region and a second region, adjacent to the first region;
a first conductive layer extending on the first region and the second region; and
a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer,wherein an upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.
1 Assignment
0 Petitions
Accused Products
Abstract
A vertical-type memory device a vertical-type memory device comprising a substrate including a first region and a second region, adjacent to the first region, a first conductive layer extending on the first region and the second region, and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.
-
Citations
20 Claims
-
1. A vertical-type memory device comprising:
-
a substrate including a first region and a second region, adjacent to the first region; a first conductive layer extending on the first region and the second region; and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer, wherein an upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A vertical-type memory device comprising:
-
a substrate including a cell array region and a connection region adjacent to the cell array region; a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region; a plurality of channel structures in the cell array region, the plurality of channel structures passing through the plurality of gate electrode layers; and a plurality of dummy channel structures in the connection region, the plurality of dummy channel structures passing through at least one of the plurality of gate electrode layers, wherein an upper surface of the substrate has a step portion at a boundary between the cell array region and the connection region, and a vertical length of the plurality of channel structures is greater than a vertical length of the plurality of dummy channel structures. - View Dependent Claims (13, 14, 15, 16)
-
-
17. A vertical-type memory device comprising:
-
a substrate including a cell array region and a connection region adjacent to the cell array region; a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region; a plurality of channel structures in the cell array region, and passing through the plurality of gate electrode layers; and a plurality of dummy channel structures in the connection region, and passing through at least one of the plurality of gate electrode layers, wherein an upper surface of the substrate has a step portion at a boundary between the cell array region and the connection region, and each of the plurality of channel structures includes a first epitaxial layer in contact with the substrate, each of the plurality of dummy channel structures includes a second epitaxial layer in contact with the substrate, and a height of an upper surface of the first epitaxial layer is different from a height of an upper surface of the second epitaxial layer. - View Dependent Claims (18, 19, 20)
-
Specification