SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20190326321A1
• Filed: 07/01/2019
• Published: 10/24/2019
• Est. Priority Date: 07/06/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Sung Gil, KIM, Seul Ye, KIM, Hong Suk, NOH, Jin Tae, CHOI, Ji Hoon, AHN, Jae Young
• Granted Patent: US 10,600,806 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 25/065 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1434 Memory
• CPC Class Codes: H01L 2924/1436 Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/14511 EEPROM
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.

Claims

1. A method of fabricating a semiconductor device comprising:

forming a channel hole penetrating a molded structure formed on a substrate;

forming a preliminary channel layer on a side surface of the channel hole;

forming a preliminary filling layer on the preliminary channel layer to fill the channel hole;

forming a first recess in the channel hole by removing a part of each of the preliminary channel layer and the preliminary filling layer, wherein a channel layer and a filling layer are formed in the forming of the first recess;

forming a spacer on a side surface of the first recess, the spacer having a bottom hole exposing an upper surface of the filling layer;

removing the filling layer completely via the bottom hole;

forming a preliminary passivation layer to fill the bottom hole;

forming a second recess by removing a part of the preliminary passivation layer and a part of the spacer; and

forming a pad to fill the second recess.

2. The method of claim 1,

wherein the forming of the spacer comprises:

forming a spacer layer to cover the side surface and a bottom surface of the first recess, and

etching the spacer layer to form the spacer.

3. The method of claim 1,

wherein a width of the bottom hole is smaller than a width of the preliminary filling layer.

4. The method of claim 1,

wherein the preliminary passivation layer is formed along a surface of the spacer and a surface of the channel layer.

5. The method of claim 1,

wherein the forming of the preliminary passivation layer comprises:

forming an air gap surrounded by the preliminary passivation layer.

6. The method of claim 1,

wherein the pad and the spacer have a same material.

7. The method of claim 1,

wherein the forming of the molded structure comprises:

alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on the substrate.

8. The method of claim 7, further comprising:

forming a trench exposing side surfaces of the sacrificial layers and the interlayer insulating layers; and

replacing the sacrificial layers with conductive layer patterns via the trench.

9. The method of claim 8, further comprising:

forming a bit line on the pad.

10. A method of fabricating a semiconductor device comprising:

forming a channel hole penetrating a molded structure formed on a substrate;

forming a preliminary channel layer on a side surface of the channel hole;

forming a preliminary filling layer on the preliminary channel layer to fill the channel hole;

forming a first recess in the channel hole by removing a part of each of the preliminary channel layer and the preliminary filling layer, wherein a channel layer and a filling layer are formed in the forming of the first recess;

forming a spacer on a side surface of the first recess, the spacer having a bottom hole exposing an upper surface of the filling layer;

removing the filling layer completely via the bottom hole; and

forming a preliminary passivation layer in the bottom hole and the channel hole, wherein an air gap is formed to be surrounded by the preliminary passivation layer in the channel hole.

11. The method of claim 10, further comprising:

after forming a preliminary passivation layer,

forming a second recess by removing a part of the preliminary passivation layer and a part of the spacer, wherein a passivation layer is formed in the channel layer and the bottom hole; and

forming a pad to fill the second recess.

12. The method of claim 11,

wherein the pad and the spacer have a same material.

13. The method of claim 10,

wherein the forming of the spacer comprises:

forming a spacer layer to cover the side surface and a bottom surface of the first recess, and

etching the spacer layer to form the spacer.

14. The method of claim 10,

wherein the preliminary passivation layer is formed along a surface of the spacer and a surface of the channel layer.