SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20190326323A1
• Filed: 07/03/2019
• Published: 10/24/2019
• Est. Priority Date: 12/19/2016
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: PARK, Min Woo, CHO, Kyo Yeon
• Granted Patent: US 10,910,400 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. The method may include forming recess areas by removing the material layers exposed through a slit passing through the preliminary stack structure. The method may include forming a data storage layer in the recess areas through the slit. The thickness of the data storage layer may be formed regardless of a size of the channel hole.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked;

forming recess areas by removing the material layers exposed through a slit passing through the preliminary stack structure;

forming a data storage layer in the recess areas through the slit;

partially removing the data storage layer through the slit such that a data storage pattern remains on a sidewall of each of the recess areas adjacent to the tunnel insulating layer; and

forming a blocking insulating layer on the data storage pattern through the slit.

2. The method according to claim 1, wherein the partially removing of the data storage layer comprises:

forming a sacrificial layer on the data storage layer;

partially removing the sacrificial layer such that a sacrificial pattern remains on the sidewall of each of the recess areas adjacent to the tunnel insulating layer; and

etching the data storage layer using the sacrificial pattern as an etching mask.

3. The method according to claim 2,

wherein the forming of the sacrificial layer comprises successively forming a first sacrificial layer and a second sacrificial layer on the data storage layer,

wherein the partially removing of the sacrificial layer comprises partially removing the first sacrificial layer and the second sacrificial layer such that the first sacrificial layer and the second sacrificial layer respectively remain as a first sacrificial pattern and a second sacrificial pattern on the sidewall of each of the recess areas adjacent to the tunnel insulating layer, and removing the second sacrificial pattern, and

wherein the etching of the data storage layer comprises partially etching the data storage layer using the first sacrificial pattern as an etching mask.

4. The method according to claim 3, further comprising, after the etching of the data storage layer,

removing the first sacrificial pattern.

5. The method according to claim 4,

wherein a first opening is formed in each of the recess areas by the partially etching of the data storage layer,

wherein a second opening is formed in each of the recess areas by the removing of the first sacrificial pattern, and

wherein the blocking insulating layer is formed on the data storage pattern over the first and second openings.

6. The method according to claim 3, wherein the first sacrificial layer has an etching selectivity different from an etching selectivity of the data storage layer.

7. The method according to claim 3, wherein the second sacrificial layer has an etching selectivity different from an etching selectivity of the first sacrificial layer.

8. The method according to claim 3, wherein the second sacrificial layer has an etching selectivity different from an etching selectivity of the data storage layer.

9. The method according to claim 3, wherein the partially removing of the first sacrificial layer and the second sacrificial layer comprises alternately cleaning the second sacrificial layer and the first sacrificial layer.

10. The method according to claim 3, wherein the partially removing of the first sacrificial layer and the second sacrificial layer comprises removing horizontal components of the first and second sacrificial layers from the recess area.

11. The method according to claim 1,

wherein the tunnel insulating layer is formed on an inner surface of the channel hole through the channel hole, and

wherein a channel layer is further formed on the tunnel insulating layer through the channel hole.

12. The method according to claim 1, wherein the forming of the recess areas comprises, after the removing of the material layers, removing portions of the interlayer insulating layers and portions of a sidewall of the tunnel insulating layer exposed through open areas from which the material layers have been removed.