MANUFACTURING METHOD FOR A TFT ARRAY SUBSTRATE AND TFT ARRAY SUBSTRATE

• US 20190326335A1
• Filed: 09/18/2018
• Published: 10/24/2019
• Est. Priority Date: 04/20/2018
• Status: Active Grant

• Current Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Liu, Guanghui, He, Peng, Xu, Yong, Ai, Fei
• Granted Patent: US 10,971,530 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate

Abstract

A manufacturing method for TFT array substrate and TFT array substrate are disclosed. After depositing an electrode material layer and a metal material layer on the gate insulation layer and the active layer in sequence after the active layer above the gate electrode is formed. A photoresist pattern is formed on the metal material layer. The photoresist pattern includes a first and second photoresist blocks with different thicknesses. The metal material layer and the electrode material layer are etched using the photoresist pattern to form a contact electrode and pixel electrodes connected with two ends of the active layer and the source/drain electrodes on the contact electrode. The process is simple and can effectively reduce the contact resistance between the source/drain and the active layer and improve the quality of the product.

Claims

1. A manufacturing method for a TFT array substrate, comprising steps of:

step S1, providing a substrate, forming a gate electrode and a gate insulation layer covering the gate electrode on the substrate;

step S2, forming an active layer on the gate insulation layer;

step S3, sequentially depositing an electrode material layer and a metal material layer on the gate insulation layer and the active layer;

forming a photoresist pattern on the metal material layer, wherein, the photoresist pattern includes a first photoresist block and a second photoresist block which are separately;

a projection of a portion of the first photoresist block in a vertical direction is overlapped with one end of the active layer, and a projection of a portion of the second photoresist block in the vertical direction is overlapped with the other end of the active layer;

a thickness of the first photoresist block is greater than a thickness of the second photoresist block; and

step S4, etching the metal material layer and the electrode material layer using the photoresist pattern as a mask to remove a portion of the metal material layer and the electrode material layer that are not covered by the photoresist pattern;

ashing the photoresist pattern to remove the second photoresist block;

etching the metal material layer using the photoresist pattern being ashed as a mask to remove a portion of the metal material layer that are not covered by the photoresist pattern being ashed in order to form a contact electrode and a pixel electrode respectively connected with two ends of the active layer and a source/drain electrode located on the contact electrode.

2. The manufacturing method for a TFT array substrate according to claim 1, wherein the step S4 further includes a step of removing the photoresist pattern being ashed.

3. The manufacturing method for a TFT array substrate according to claim 2, wherein the method further comprises a step S5, depositing a passivation layer on the gate insulation layer, the active layer, the pixel electrode, and the source/drain electrode;

forming the common electrode 90 on the passivation layer.

4. The manufacturing method for a TFT array substrate according to claim 1, wherein a specific process of forming the gate electrode on the substrate is:

depositing a gate metal layer on the substrate, performing an exposure and development process on the gate metal layer in order to form the gate electrode;

wherein the step S2 comprises;

step S21, depositing an amorphous silicon material on the gate insulation layer, and performing an exposure and development process to the amorphous silicon material to form an amorphous silicon island;

step S22, performing an ion doping to the amorphous silicon island to form the active layer, wherein the active layer includes an amorphous silicon material layer and a doped amorphous silicon layer located on the amorphous silicon material layer;

step S3, a specific process of forming the photoresist pattern on the metal material layer is;

forming a photoresist material layer on the metal material layer, and patterning the photoresist material layer using a halftone mask in order to obtain the photoresist pattern.

5. The manufacturing method for a TFT array substrate according to claim 4, wherein in the step S4, when etching the metal material layer and the electrode material layer using the photoresist pattern as a mask in order to remove the metal material layer and the electrode material layer which are not blocked by the photoresist pattern, at the same time, removing a portion of the doped amorphous silicon layer not covered by the photoresist pattern in order to form the first contact layer and the second contact layer respectively located on two ends of the amorphous silicon material layer, wherein the contact electrode is connected to the first contact layer, and the pixel electrode is connected to the second contact layer.

6. The manufacturing method for a TFT array substrate according to claim 5, wherein in the step S4, dry etching the metal material layer using the photoresist pattern as a mask to remove the portion of the metal material layer not covered by the photoresist pattern, and then wet etching the electrode material layer and the doped amorphous silicon layer using the photoresist pattern as a mask to remove a portion of the electrode material layer and the doped amorphous silicon layer that are not covered by the photoresist pattern;

dry etching the metal material layer using the photoresist pattern being ashed as a mask to remove a portion of the metal material layer not covered by the photoresist pattern being ashed.

7. The manufacturing method for a TFT array substrate according to claim 1, wherein a material of the gate electrode is molybdenum (Mo), a material of the gate insulation layer is silicon nitride (SiNx) and a material of the electrode material layer is indium tin oxide (ITO).

8. The manufacturing method for a TFT array substrate according to claim 4, wherein in the step S22, performing an N-type ion doping to the amorphous silicon island.

9. The manufacturing method for a TFT array substrate according to claim 4, wherein in the step S22, performing an N-type ion doping to the amorphous silicon island using phosphorus ions.

10. A TFT array substrate, comprising a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the substrate and the gate electrode, an active layer disposed on the gate insulation layer and above the gate electrode, and a contact electrode and a pixel electrode respectively connected with two terminals of the active layer, and a source/drain electrode located on the contact electrode.