SEMICONDUCTOR DEVICE HAVING RESISTANCE ELEMENTS AND FABRICATION METHOD THEREOF

• US 20190326386A1
• Filed: 07/02/2019
• Published: 10/24/2019
• Est. Priority Date: 02/19/2016
• Status: Active Grant

• Current Assignee: United Semiconductor Japan Co., Ltd. (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Ema, Taiji, Misawa, Nobuhiro, Kumeno, Kazuyuki, Yasudo, Makoto
• Granted Patent: US 10,840,323 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 28/20 Resistors

Abstract

A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration C_X. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration C_Y lower than the concentration C_X. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration C_X. A sign of a TCR of the second polycrystalline silicon changes at the concentration C_Y.

Claims

1. A semiconductor device fabrication method comprising:

acquiring a relationship between a concentration of first impurities and a temperature coefficient for a first polycrystalline silicon having a first width and a second polycrystalline silicon having a second width larger than the first width;

setting, on the basis of the relationship, a first concentration of the first impurities in the first polycrystalline silicon and a second concentration of the first impurities in the second polycrystalline silicon; and

forming the first polycrystalline silicon containing the first impurities at the first concentration and the second polycrystalline silicon containing the first impurities at the second concentration.

2. The semiconductor device fabrication method according to claim 1, wherein:

the second concentration is lower than the first concentration;

a sign of the temperature coefficient of the first polycrystalline silicon changes at the first concentration; and

a sign of the temperature coefficient of the second polycrystalline silicon changes at the second concentration.

3. The semiconductor device fabrication method according to claim 1, wherein:

the first polycrystalline silicon containing the first impurities at the first concentration has a negative temperature coefficient; and

the second polycrystalline silicon containing the first impurities at the second concentration has a positive temperature coefficient.

4. The semiconductor device fabrication method according to claim 3, wherein the second concentration is same as the first concentration.

5. The semiconductor device fabrication method according to claim 3, wherein the second concentration is lower than the first concentration.

6. The semiconductor device fabrication method according to claim 1, wherein the first concentration and the second concentration are higher than or equal to 1×

10²⁰ cm<sup>−

3</sup> and lower than or equal to 1×

10²¹ cm<sup>−

3</sup>.

7. The semiconductor device fabrication method according to claim 1, wherein:

the first polycrystalline silicon contains the first impurities at the first concentration throughout a direction perpendicular to a direction of the first width, in a plan view; and

the second polycrystalline silicon contains the first impurities at the second concentration throughout a direction perpendicular to a direction of the second width, in the plan view.

8. The semiconductor device fabrication method according to claim 1, wherein the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in series.

9. The semiconductor device fabrication method according to claim 1, wherein the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in parallel.

10. The semiconductor device fabrication method according to claim 1, wherein one end portion of the first polycrystalline silicon and one end portion of the second polycrystalline silicon are electrically connected in series.

11. The semiconductor device fabrication method according to claim 1, wherein:

one end portion of the first polycrystalline silicon and one end portion of the second polycrystalline silicon are electrically connected;

the other end portion of the first polycrystalline silicon and the other end portion of the second polycrystalline silicon are electrically connected; and

the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in parallel.

12. The semiconductor device fabrication method according to claim 1, wherein the first impurities are p-type impurities.

13. The semiconductor device fabrication method according to claim 1, wherein the first polycrystalline silicon and the second polycrystalline silicon are formed as continuous one body and electrically connected.

14. The semiconductor device fabrication method according to claim 11, wherein the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in series.

15. The semiconductor device fabrication method according to claim 1, wherein a first sheet resistance of the first polycrystalline silicon and a second sheet resistance of the second polycrystalline silicon are equal or almost equal.