SEMICONDUCTOR DEVICE

• US 20190326400A1
• Filed: 07/01/2019
• Published: 10/24/2019
• Est. Priority Date: 10/31/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LO, WEN-SHUN, CHANG, YU-CHI, TSUI, FELIX YING-KIT
• Granted Patent: US 10,763,329 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device includes a semiconductor substrate, a gate electrode, a channel region, a pair of source/drain regions and a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The channel region includes a pair of first sides opposing to each other in a channel length direction, and a pair of second sides opposing to each other in a channel width direction. The source/drain regions are adjacent to the pair of first sides of the channel region in the channel length direction. The threshold voltage adjusting region covers the pair of second sides of the channel region in the channel width direction, and exposing the pair of first sides of the channel region in the channel length direction.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a gate electrode over the semiconductor substrate;

a channel region between the semiconductor substrate and the gate electrode, wherein the channel region includes a pair of first sides opposing to each other in a channel length direction, and a pair of second sides opposing to each other in a channel width direction;

a pair of source/drain regions adjacent to the pair of first sides of the channel region in the channel length direction; and

a threshold voltage adjusting region covering the pair of second sides of the channel region in the channel width direction, and exposing the pair of first sides of the channel region in the channel length direction.

2. The semiconductor device of claim 1, wherein a depth of the threshold voltage adjusting region is greater than a depth of the pair of source/drain region.

3. The semiconductor device of claim 1, further comprising an isolation structure in the semiconductor substrate.

4. The semiconductor device of claim 3, wherein the isolation structure comprises a shallow trench isolation (STI) in a trench of the semiconductor substrate.

5. The semiconductor device of claim 3, wherein the threshold voltage adjusting region further covers a sidewall of the isolation structure.

6. The semiconductor device of claim 5, wherein the threshold voltage adjusting region further covers a bottom of the isolation structure.

7. The semiconductor device of claim 1, wherein the threshold voltage adjusting region and the channel region have the same doping type.

8. The semiconductor device of claim 1, wherein a doping concentration of the threshold voltage adjusting region is higher than a doping concentration of the channel region.

9. The semiconductor device of claim 1, wherein the channel region includes an edge region proximal to the threshold voltage adjusting region, and a central region distal to the threshold voltage adjusting region, and a first threshold voltage at the edge region is higher than a second threshold voltage of in the central region

10. A semiconductor device, comprising:

a semiconductor substrate;

an isolation structure in the semiconductor substrate;

a gate electrode over the semiconductor substrate;

a channel region between the semiconductor substrate and the gate electrode;

a pair of source/drain regions adjacent to two opposing sides of the channel region in a channel length direction; and

a threshold voltage adjusting region covering a sidewall and a bottom of the isolation structure.

11. The semiconductor device of claim 10, wherein the channel region includes a central region, and an edge region adjoining to the central region in a channel width direction.

12. The semiconductor device of claim 11, wherein a first threshold voltage of the semiconductor device at the edge region is higher than a second threshold voltage of the semiconductor device in the central region.

13. The semiconductor device of claim 11, wherein a ratio of a width of the edge region to a width of the channel region in the channel width direction is substantially in a range from about 0.02 to about 0.1.

14. The semiconductor device of claim 10, further comprising a liner insulation layer between the threshold voltage adjusting region and the isolation structure.

15. The semiconductor device of claim 10, wherein the isolation structure comprises a shallow trench isolation (STI) in a trench of the semiconductor substrate.

16. A semiconductor device, comprising:

a semiconductor substrate;

a gate electrode over the semiconductor substrate;

a channel region between the semiconductor substrate and the gate electrode;

a pair of source/drain regions adjacent to two opposing sides of the channel region in a channel length direction;

a pair of isolation structures adjacent to two opposing sides of the channel region in a channel width direction, and extending along the channel length direction; and

a pair of threshold voltage adjusting regions between the channel region and the pair of isolation structures respectively, wherein the pair of threshold voltage adjusting regions and the channel region have the same doping type, and the pair of threshold voltage adjusting regions extend along the channel length direction.

17. The semiconductor device of claim 16, wherein the pair of threshold voltage adjusting regions are separated by the channel region.

18. The semiconductor device of claim 16, wherein a doping concentration of the pair of threshold voltage adjusting regions is higher than a doping concentration of the channel region.

19. The semiconductor device of claim 16, wherein the pair of threshold voltage adjusting regions further extend to bottoms of the pair of isolation structures, respectively.

20. The semiconductor device of claim 16, further comprising a pair of liner insulation layers between the pair of threshold voltage adjusting regions and the pair of isolation structures, respectively.