HETEROJUNCTION BIPOLAR TRANSISTORS WITH AN INVERTED CRYSTALLINE BOUNDARY IN THE BASE LAYER

• US 20190326411A1
• Filed: 04/24/2018
• Published: 10/24/2019
• Est. Priority Date: 04/24/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Jain, Vibhor, Dongmo, Pernell, Luce, Cameron, Adkisson, James W., Liu, Qizhi
• Granted Patent: US 10,818,772 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0817 of heterojunction bipolar transistors H01L29/7375 takes precedence
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/7373 having a two-dimensional base, e.g. modulation-doped base, inversion layer base, delta-doped base
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Abstract

Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.

Claims

1. A structure for a heterojunction bipolar transistor, the structure comprising:

a trench isolation region surrounding an active region of semiconductor material;

a collector in the active region;

a base layer including a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section;

an emitter arranged over the second section of the base layer; and

an extrinsic base layer arranged over the first section of the base layer and the third section of the base layer, the extrinsic base layer including a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material, and the first section of the extrinsic base layer intersecting the second section of the extrinsic base layer along an interface that extends over the trench isolation region.

2. The structure of claim 1 wherein the active region includes a top surface, and the interface is inclined at an angle of greater than 90°

relative to the top surface of the active region.

3. The structure of claim 2 wherein the active region includes a top surface, the trench isolation region includes a top surface that is coplanar with the top surface of the active region, and the interface is inclined at an angle of less than 90°

relative to the top surface of the trench isolation region.

4. The structure of claim 2 wherein the interface extends into the base layer and is arranged between the first section of the base layer and the third section of the base layer, the first section of the base layer contains polycrystalline semiconductor material, and the third section of the base layer contains single-crystal semiconductor material.

5. The structure of claim 4 wherein the trench isolation region includes a surface adjacent to the active region that intersects the top surface at a corner, and the interface has a first end point arranged over the top surface of the trench isolation region and a second end point arranged at the corner.

6. The structure of claim 1 wherein the trench isolation region includes a top surface that is coplanar with the top surface of the active region, and the interface is inclined at an angle of less than 90°

relative to the top surface of the trench isolation region.

7. The structure of claim 1 wherein the interface extends into the base layer and is arranged between the first section of the base layer and the third section of the base layer, and the first section of the base layer contains polycrystalline semiconductor material and the third section of the base layer contains single-crystal semiconductor material.

8. The structure of claim 7 wherein the trench isolation region includes a top surface and a surface adjacent to the active region that intersects the top surface at a corner, and the interface has a first end point arranged over the trench isolation region and a second end point arranged at the corner.

9. The structure of claim 1 further comprising:

a silicide layer over the extrinsic base layer,

wherein the first section of the extrinsic base layer is arranged between the silicide layer and the base layer.

10. The structure of claim 9 wherein the interface is arranged between the silicide layer and the base layer.

11. The structure of claim 1 further comprising:

a sidewall spacer surrounding the emitter.

12. A method for fabricating a heterojunction bipolar transistor, the method comprising:

forming a trench isolation region surrounding an active region of semiconductor material that includes a collector;

epitaxially growing a base layer that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section;

forming an emitter arranged over the second section of the base layer; and

epitaxially growing an extrinsic base layer arranged over the first section of the base layer and the third section of the base layer,

wherein the extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material, and the first section of the extrinsic base layer intersects the second section of the extrinsic base layer along an interface that extends over the trench isolation region.

13. The method of claim 12 wherein the active region includes a top surface, and the interface is inclined at an angle of greater than 90°

relative to the top surface of the active region.

14. The method of claim 13 wherein the interface extends into the base layer and is arranged between the first section of the base layer and the third section of the base layer, the first section of the base layer contains polycrystalline semiconductor material, and the third section of the base layer contains single-crystal semiconductor material.

15. The method of claim 14 wherein the trench isolation region includes a surface adjacent to the active region that intersects the top surface at a corner, and the interface has a first end point arranged over the top surface of the trench isolation region and a second end point arranged at the corner.

16. The method of claim 12 further comprising:

implanting ions of a dopant into the extrinsic base layer.

17. The method of claim 12 wherein the interface extends into the base layer and is arranged between the first section of the base layer and the third section of the base layer, and the first section of the base layer contains polycrystalline semiconductor material and the third section of the base layer contains single-crystal semiconductor material.

18. The method of claim 17 wherein the trench isolation region includes a top surface and a surface adjacent to the active region that intersects the top surface at a corner, and the interface has a first end point arranged over the trench isolation region and a second end point arranged at the corner.

19. The method of claim 12 further comprising:

forming a sidewall spacer that surrounds the emitter.

20. The method of claim 12 further comprising:

forming a silicide layer over the extrinsic base layer,

wherein the first section of the extrinsic base layer and the interface are arranged between the silicide layer and the base layer.