METHOD FOR PRODUCING A TRANSISTOR

• US 20190326412A1
• Filed: 11/30/2017
• Published: 10/24/2019
• Est. Priority Date: 12/09/2016
• Status: Active Grant

• Current Assignee: United Monolithic Semiconductors GmbH (Thales SA)
• Original Assignee: United Monolithic Semiconductors GmbH (Thales SA)
• Inventors: BEHAMMER, Dag
• Granted Patent: US 10,714,589 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A method produces a transistor, in particular a gallium nitride transistor based on high electron mobility. After a structured metal layer has been formed in a first gate region by a temporarily formed structured first photoresist layer, an intermediate layer has been deposited and a second insulation layer has been deposited, a second photoresist layer is structured in order to expose a second gate region, wherein subsequently a first field plate and a second field plate are formed as buried field plates on respective sides of the second gate region.

Claims

1. A method for production of a transistor, in particular of a gallium-nitride transistor based on high electron mobility, in which the following steps are carried out:

making available a substrate, which has multiple active layers on a carrier material, above which layers contact regions for a drain contact and a source contact are configured, wherein the region between the source contact and the drain contact is covered with a first insulation layer,

forming a structured metal layer in a first gate region, by means of a temporarily formed structured first photoresist layer,

depositing a second insulation layer,

depositing an intermediate layer,

structuring a second photoresist layer, so as to expose a second gate region, the lateral expanse of which is smaller than that of the first gate region,

removing the first intermediate layer, the second insulation layer, and the metal layer in the second gate region by means of the second photoresist layer, so that a first field plate and a second field plate are formed on both sides of the second gate region,

removing the second photoresist layer,

forming lateral spacers that narrow toward one another toward the substrate surface in the second gate region, and

forming a gate electrode after partial removal of the first insulation layer, with a gate foot between the spacers and a gate head that partially covers the metal layer and the first insulation layer.

2. The method according to claim 1, in which the step of formation of the spacers that run toward one another takes place by means of deposition of a further insulation layer, wherein the further insulation layer is etched using the intermediate layer for end-point recognition.

3. The method according to claim 1, in which the step of formation of the spacers that run toward one another takes place before removal of the first insulation layer.

4. The method according to claim 1, in which the step of formation of the spacers that run toward one another takes place after removal of the first insulation layer in the second gate region.

5. The method according to claim 1, in which the metal layer is used as a selective etch stop layer during removal of the intermediate layer and the second insulation layer in the second gate region.

6. The method according to claim 5, in which the metal layer is structured by means of the structured second photoresist layer or by means of the structured intermediate layer and second insulation layer in the second gate region.

7. The method according to claim 5, in which the metal layer in the second gate region is etched selectively relative to the first insulation layer.

8. The method according to claim 1, in which the intermediate layer is formed from silicon oxide.

9. The method according to claim 1, in which the first insulation layer, the second insulation layer, and the further insulation layer are formed from silicon nitride.

10. The method according to claim 1, in which the first gate region and the second gate region are disposed in such a manner that the first field plate, which faces in the direction toward the drain contact, is formed with a dimension of typically approximately 300 nm to 500 nm.

11. The method according to claim 1, in which the first gate region and the second gate region are disposed in such a manner that the second field plate, which faces in the direction toward the source contact, is formed with a minimal dimension.

12. The method according to claim 1, in which the first insulation layer is formed with a thickness of approximately 20 nm to 50 nm.