Methods, Apparatus, and System for Reducing Leakage Current in Semiconductor Devices

• US 20190326413A1
• Filed: 04/24/2018
• Published: 10/24/2019
• Est. Priority Date: 04/24/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Malinowski, Arkadiusz, Singh, Jagar
• Granted Patent: US 10,546,943 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.

Claims

1. A method, comprising:

forming a semiconductor substrate comprising a well region containing a first impurity;

forming a gate on the semiconductor substrate above the well region;

implanting at least one second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first impurity concentration;

removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions, wherein the depletion regions are essentially not disposed on sides of the S/D cavities; and

growing epitaxially a doped S/D region in each S/D cavity, wherein each doped S/D region comprises at least one third impurity of the same type as the at least one second impurity, wherein each doped S/D region has a second impurity concentration greater than the first impurity concentration.

2. The method of claim 1, wherein the first impurity is a p-type impurity and the at least one second impurity and the at least one third impurity are n-type impurities.

3. The method of claim 1, wherein the first impurity is an n-type impurity and the at least one second impurity and the at least one third impurity are p-type impurities.

4. The method of claim 1, wherein the implanting the at least one second impurity comprises tilting the semiconductor substrate, exposing the semiconductor substrate to the at least one second impurity in a first direction, rotating the semiconductor substrate 180°

, and exposing the semiconductor substrate to the at least one second impurity in a second direction.

5. The method of claim 1, wherein each depletion region has a crescent cross section.

6. The method of claim 1, wherein each depletion region has a rectangular cross section.

7. The method of claim 1, wherein removing the upper portion of each second impurity region comprises performing a reactive ion etch (RIE).

8. A semiconductor device, comprising:

a semiconductor substrate;

a well region comprising a first impurity and disposed in the semiconductor substrate;

a gate on the semiconductor substrate above the well region;

two doped S/D regions comprising at least one third impurity and disposed in the semiconductor substrate, one on each side of the gate; and

two depletion regions, one below each doped S/D region and essentially not disposed on sides of each S/D region, each depletion region comprising at least one second impurity at a concentration below the concentration of the at least one third impurity in the doped S/D regions, wherein the first impurity is of a first type and the at least one second impurity and the at least one third impurity are of a second type opposite the first type.

9. The semiconductor device of claim 8, wherein the first impurity is a p-type impurity and the at least one second impurity and the at least one third impurity are n-type impurities.

10. The semiconductor device of claim 8, wherein the first impurity is an n-type impurity and the at least one second impurity and the at least one third impurity are p-type impurities.

11. The semiconductor device of claim 8, wherein each depletion region has a crescent cross section.

12. The semiconductor device of claim 8, wherein each depletion region has a rectangular cross section.

13. A system, comprising:

a semiconductor device processing system to manufacture a semiconductor device; and

a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of the semiconductor device processing system;

wherein the semiconductor device processing system is adapted to;

form a semiconductor substrate comprising a well region containing a first impurity;

form a gate on the semiconductor substrate above the well region;

implant at least one second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first impurity concentration;

remove an upper portion of each of the two second impurity regions, to yield two source/drain (S/D) cavities above two depletion regions, wherein the depletion regions are essentially not disposed on sides of the S/D cavities; and

grow epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises at least one third impurity of the same type as the at least one second impurity, wherein each doped S/D region has a second impurity concentration greater than the first impurity concentration.

14. The system of claim 13, wherein the semiconductor device processing system is adapted to use a p-type impurity as the first impurity and an n-type impurity as the at least one second impurity and the at least one third impurity.

15. The system of claim 13, wherein the semiconductor device processing system is adapted to use an n-type impurity as the first impurity and a p-type impurity as the at least one second impurity and the at least one third impurity.

16. The system of claim 13, wherein the semiconductor device processing system is adapted to implant the at least one second impurity by tilting the semiconductor substrate, exposing the semiconductor substrate to the at least one second impurity in a first direction, rotating the semiconductor substrate 180°

, and exposing the semiconductor substrate to the at least one second impurity in a second direction.

17. The system of claim 13, wherein the semiconductor device processing system is adapted to form each depletion region to have a crescent cross section.

18. The system of claim 13, wherein the semiconductor device processing system is adapted to form each depletion region to have a rectangular cross section.

19. The system of claim 13, wherein the semiconductor device processing system is adapted to remove the upper portion of each second impurity region by performing a reactive ion etch (RIE).