SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20190326419A1
• Filed: 07/01/2019
• Published: 10/24/2019
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: PENG, Cheng-Yi, YEH, Chih Chieh, CHANG, Chih-Sheng, CHIANG, Hung-Li, CHEN, Hung-Ming, YEO, Yee-Chia
• Granted Patent: US 11,145,750 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Claims

1. A semiconductor device comprising:

a fin structure disposed over a substrate, the fin structure extending in a first direction and including an upper layer, part of the upper layer being exposed from an isolation insulating layer;

a gate structure disposed over part of the fin structure, the gate structure extending in a second direction perpendicular to the first direction;

a source/drain structure which includes part of the fin structure not covered by the gate structure;

an interlayer dielectric layer formed over the fin structure, the gate structure and the source/drain structure;

a contact hole formed in the interlayer dielectric layer exposing the source/drain structure; and

a contact material disposed in the contact hole, wherein;

the contact material includes a silicon phosphide layer and a metal layer, and

the silicon phosphide layer covers the source/drain structure, an upper surface of the isolation insulating layer, and sidewalls of the interlayer dielectric layer.

2. The semiconductor device of claim 1, further comprising an alloy layer between the silicon phosphide layer and the metal layer.

3. The semiconductor device of claim 2, wherein the alloy layer is a silicide.

4. The semiconductor device of claim 1, wherein the fin structure is made of germanium or a germanium compound.

5. The semiconductor device of claim 1, wherein the source/drain structure includes germanium phosphide.

6. The semiconductor device of claim 1, wherein the metal layer comprises a single layer or multiple layers including Co, W, Ti, Ta, Cu, Al, or Ni.

7. The semiconductor device of claim 1, wherein the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer.

8. The semiconductor device of claim 7, wherein the first dielectric layer is an etch stop layer.

9. A semiconductor device comprising:

a fin structure disposed over a substrate, the fin structure extending in a first direction and including an upper layer, part of the upper layer being exposed from an isolation insulating layer;

a gate structure disposed over part of the fin structure, the gate structure extending in a second direction perpendicular to the first direction;

a source/drain structure which includes a first portion part of the fin structure not covered by the gate structure;

an interlayer dielectric layer formed over a second portion of the fin structure;

a cap layer disposed over the source/drain structure and sidewalls of the interlayer dielectric layer;

a high-k dielectric layer disposed over the cap layer; and

an electrically conductive layer disposed over the high-k dielectric layer.

10. The semiconductor device of claim 9, wherein the cap layer includes silicon phosphide.

11. The semiconductor device of claim 9, wherein the fin structure is made of germanium or a germanium compound.

12. The semiconductor device of claim 9, wherein the source/drain structure includes germanium phosphide.

13. The semiconductor device of claim 9, wherein the high-k dielectric layer includes a silicon nitride, an aluminum oxide, or a lanthanum oxide.

14. The semiconductor device of claim 9, wherein the electrically conductive layer comprises a single layer or multiple layers including Co, W, Ti, Ta, Cu, Al, or Ni.

15. A semiconductor device comprising:

a fin structure disposed over a substrate, the fin structure extending in a first direction and including an upper layer, part of the upper layer being exposed from an isolation insulating layer;

a gate structure disposed over part of the fin structure, the gate structure extending in a second direction perpendicular to the first direction;

a source/drain structure disposed over a part of the fin structure not covered by the gate structure;

an interlayer dielectric layer formed over the fin structure;

an epitaxial layer disposed over sidewalls of the interlayer dielectric layer and an upper surface of the isolation insulating layer;

a cap layer disposed over the epitaxial layer and the source/drain structure;

a high-k dielectric layer disposed over the cap layer; and

a metal layer disposed over high-k dielectric layer.

16. The semiconductor device of claim 15, wherein the epitaxial layer includes germanium phosphide.

17. The semiconductor device of claim 15, wherein the cap layer includes silicon phosphide.

18. The semiconductor device of claim 15, wherein the high-k dielectric layer includes a silicon nitride, an aluminum oxide, or a lanthanum oxide.

19. The semiconductor device of claim 15, wherein the metal layer comprises a single layer or multiple layers including Co, W, Ti, Ta, Cu, Al, or Ni.

20. The semiconductor device of claim 15, wherein the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer, and the first dielectric layer is an etch stop layer.