GALLIUM NITRIDE TRANSISTOR WITH IMPROVED TERMINATION STRUCTURE

• US 20190326427A1
• Filed: 04/23/2019
• Published: 10/24/2019
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel M., Hamdan, Maher J.
• Granted Patent: US 10,847,644 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/10 with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate

Abstract

A gallium nitride transistor includes one or more P-type hole injection structures that are positioned between the gate and the drain. The P-type hole injection structures are configured to inject holes in the transistor channel to combine with trapped carriers (e.g., electrons) so the electrical conductivity of the channel is less susceptible to previous voltage potentials applied to the transistor.

Claims

1. A transistor comprising:

a semiconductor substrate;

a source region formed in the substrate and including a source electrode in contact with a portion of the substrate;

a drain region formed in the substrate and separated from the source region;

a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region;

a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region;

a dielectric layer formed over and in contact with a first portion of the P-type layer; and

a continuous metal layer that is (1) formed over and in contact with the drain region of the substrate to form a drain electrode, (2) formed over and in contact with a second portion of the P-type layer to form a hole injection electrode, and (3) formed over and in contact with a portion of the dielectric layer to form a field plate for the hole injection region.

2. The transistor of claim 1 wherein the continuous metal layer extends across the drain region of the substrate, abuts a first side surface of the P-type layer and extends across a first region of a top surface of the P-type layer.

3. The transistor of claim 2 wherein the dielectric layer extends across a surface of the substrate, abuts a second side surface of the P-type layer and extends across a second region of the top surface of the P-type layer.

4. The transistor of claim 3 wherein the field plate extends across the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer.

5. The transistor of claim 1 wherein the continuous metal layer is in ohmic contact with the P-type layer.

6. The transistor of claim 1 further comprising a plurality of individual hole injection regions formed along a length of the drain region.

7. The transistor of claim 1 wherein the hole injection region is a first hole injection region and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region.

8. The transistor of claim 7 wherein the second hole injection region includes a P-type layer that is in contact with a portion of the substrate and is not in ohmic contact with the continuous metal layer.

9. The transistor of claim 1 wherein the continuous metal layer is formed over approximately one half of a top surface of the P-type layer and the dielectric layer is formed over a remaining portion of the top surface of the P-type layer.

10. The transistor of claim 1 wherein the semiconductor substrate comprises gallium nitride.

11. A transistor comprising:

a semiconductor substrate;

a source region formed in the substrate and including a source electrode in contact with a portion of the substrate;

a drain region formed in the substrate and separated from the source region;

a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region;

a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region;

a dielectric layer extending across a first region of a top surface of the P-type layer; and

a metal layer that (1) extends across a drain region of the substrate to form a drain electrode, (2) extends across a second region of the top surface of the P-type layer to form a hole injection electrode, and (3) extends across a portion of the dielectric layer to form a field plate.

12. The transistor of claim 11 wherein the field plate is a hole injection region field plate.

13. The transistor of claim 11 wherein the metal layer extends across the drain region of the substrate, abuts a first side surface of the P-type layer and extends across the second region of the top surface of the P-type layer to form the hole injection electrode.

14. The transistor of claim 13 wherein the dielectric layer extends across a surface of the substrate, abuts a second side surface of the P-type layer and extends across the first region of the top surface of the P-type layer.

15. The transistor of claim 14 wherein the field plate extends across the first region of the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer.

16. The transistor of claim 11 wherein the metal layer is in ohmic contact with the P-type layer.

17. The transistor of claim 11 further comprising a plurality of individual hole injection regions formed along a length of the drain region.

18. The transistor of claim 11 wherein the hole injection region is a first hole injection region and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region.

19. The transistor of claim 18 wherein the second hole injection region includes a P-type layer that is in contact with a portion of the substrate and is not in ohmic contact with the continuous metal layer.

20. A transistor comprising:

a semiconductor substrate;

a source region formed in the substrate and including a source electrode in contact with a portion of the substrate;

a drain region formed in the substrate and separated from the source region;

a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region;

a floating hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region.