SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20190326433A1
• Filed: 04/03/2019
• Published: 10/24/2019
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: SUMIDA, Wataru
• Granted Patent: US 11,043,585 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Reliability of a semiconductor device is improved. The semiconductor device including a first MISFET group of a plurality of first MISFETs and a second MISFET group of a plurality of second MISFETs has a plurality of trenches each formed in a semiconductor layer and formed of an upper trench part and a lower trench part, and a plurality of gate electrodes formed inside the plurality of trenches. A thinner gate insulator is formed to the upper trench part and a thicker field insulator is formed to the lower trench part. In a trench at the outermost position in the first MISFET group and a trench at the outermost position in the second MISFET group, the gate insulator is not formed in the upper trench part, but the field insulator is formed in the upper trench part and the lower trench part.

Claims

1. A semiconductor device having a first region in which a plurality of first MISFETs are formed and a second region in which a plurality of second MISFETs are formed,

the semiconductor device comprising:

a semiconductor layer;

a plurality of trenches formed in the semiconductor layer in the first region and the second region; and

a plurality of gate electrodes formed inside the plurality of trenches in the first region and the second region,

wherein each of the plurality of trenches has an upper trench part and a lower trench part that is positioned lower than the upper trench part,

among the plurality of trenches in the first region, a first insulator is formed to the upper trench part and the lower trench part in a first outermost trench that is the closest to the second region, and,

in each of the plurality of trenches in the first region other than the first outermost trench, a second insulator having a thickness smaller than that of the first insulator is formed to the upper trench part and the first insulator is formed to the lower trench part.

2. The semiconductor device according to claim 1,

wherein, among the plurality of trenches in the second region, the first insulator is formed to the upper trench part and the lower trench part in the second outermost trench that is the closest to the first region, and

in each of the plurality of trenches in the second region other than the second outermost trench, the second insulator is formed to the upper trench part, and the first insulator is formed to the lower trench part.

3. The semiconductor device according to claim 2,

wherein each of the plurality of first MISFETs and the plurality of second MISFETs configures a part of a bidirectional switch.

4. The semiconductor device according to claim 3, further comprising:

a plurality of channel regions formed in the semiconductor layer in the first region and the second region;

a plurality of source regions formed in the plurality of channel regions in the first region and the second region;

a first source wiring electrically coupled to the plurality of source regions in the first region;

a second source wiring electrically coupled to the plurality of source regions in the second region;

a first gate wiring electrically coupled to at least a part of the plurality of gate electrodes in the first region; and

a second gate wiring electrically coupled to at least a part of the plurality of gate electrodes in the second region.

5. The semiconductor device according to claim 4,

wherein each of the semiconductor layer and the plurality of source regions has an n-type conductivity, and

each of the plurality of channel regions has a p-type conductivity.

6. The semiconductor device according to claim 4,

wherein, in a plan view, each of the first source wiring and the second source wiring is formed in a comb-teeth like shape,

in a plan view, comb teeth of the first source wiring and comb teeth of the second source wiring are formed to engage each other,

the plurality of first MISFETs are formed below the first source wiring, and

the plurality of second MISFETs are formed below the second source wiring.

7. The semiconductor device according to claim 4,

wherein the gate electrode formed inside the first outermost trench is electrically coupled to the first source wiring, and

the gate electrode formed inside the second outermost trench is electrically coupled to the second source wiring.

8. The semiconductor device according to claim 1,

wherein a width of the lower trench part is larger than that of the upper trench part.

9. A method of manufacturing a semiconductor device having a first region in which a plurality of first MISFETs are formed and a second region in which a plurality of second MISFETs are formed,

the method comprising the steps of:

(a) forming a semiconductor layer on a semiconductor substrate in the first region and the second region;

(b) forming a plurality of first insulators on the semiconductor layer in the first region and the second region,

(c) forming a plurality of upper trench parts in the semiconductor layer by performing an etching process using the plurality of first insulators as masks;

(d) selectively forming a plurality of second insulators on side surfaces of the plurality of upper trench parts;

(e) forming a plurality of lower trench parts in the semiconductor layer by performing an etching process using the plurality of first insulators and the plurality of second insulators as masks so that a plurality of trenches made of the plurality of upper trench parts and the plurality of lower trench parts are formed;

(f) forming a plurality of third insulator to the plurality of lower trench parts;

(g) forming a fourth insulator to each surface of the plurality of first insulators, the plurality of second insulators, and the plurality of third insulators;

(h) forming a resist pattern having a pattern to open a first outermost trench that is the closest to the second region among the plurality of trenches in the first region and to open a second outermost trench that is the closest to the first region among the plurality of trenches in the second region;

(i) removing a part of the fourth insulator by performing an etching process using the resist pattern as a mask;

(j) removing the resist pattern after the step (i);

(k) removing the plurality of second insulators formed inside the first outermost trench and the second outermost trench and the plurality of first insulators not covered by the fourth insulator after the step (j);

(l) removing the third insulator and the fourth insulator after the step (k);

(m) forming a plurality of fifth insulators to the upper trench part and the lower trench part in the first outermost trench, to the upper trench part and the lower trench part in the second outermost trench, and also to the plurality of lower trench parts in the plurality of trenches other than the first outermost trench and the second outermost trench after the step (l);

(n) removing the first insulator and the second insulator after the step (m);

(o) forming a plurality of sixth insulators having a thickness smaller than that of the fifth insulator to the plurality of upper trench parts in the plurality of trenches other than the first outermost trench and the second outermost trench after the step (n); and

(p) forming a plurality of gate electrodes inside the plurality of trenches including the first outermost trench and the second outermost trench after the step (o).

10. The method of manufacturing a semiconductor device according to claim 9,

wherein the resist pattern in the step (h) is also configured to open a region between the first outermost trench and the second outermost trench.

11. The method of manufacturing a semiconductor device according to claim 10,

wherein, in a plan view, the first region and the second region are alternately arranged.

12. The method of manufacturing a semiconductor device according to claim 9,

wherein the plurality of first insulators and the plurality of second insulators are formed of silicon nitride, and

the plurality of third insulators and the fourth insulator are formed of silicon oxide.

13. The method of manufacturing a semiconductor device according to claim 12,

wherein the step (l) is performed using a solution containing hydrofluoric acid, and

the step (k) and the step (n) are performed using a solution containing phosphoric acid.

14. The method of manufacturing a semiconductor device according to claim 9, further comprising the steps of:

(q) forming a plurality of channel regions in the semiconductor layer in the first region and the second region;

(r) forming a plurality of source regions to the plurality of channel regions in the first region and the second region; and

(s) forming a first source wiring electrically coupled to the plurality of source regions in the first region, a second source wiring electrically coupled to the plurality of source regions in the second region, a first gate wiring electrically coupled to at least apart of the plurality of gate electrodes in the first region, and a second gate wiring electrically coupled to at least a part of the plurality of gate electrodes in the second region.

15. The method of manufacturing a semiconductor device according to claim 14,

wherein each of the semiconductor layer and the plurality of source regions has an n-type conductivity, and

each of the plurality of channel regions has a p-type conductivity.

16. The method of manufacturing a semiconductor device according to claim 14,

wherein the gate electrode formed inside the first outermost trench is electrically coupled to the first source wiring, and

the gate electrode formed inside the second outermost trench is electrically coupled to the second source wiring.

17. The method of manufacturing a semiconductor device according to claim 9,

wherein, in the step (f), a width of each of the plurality of lower trench parts is larger than that of each of the plurality of upper trench parts.

18. A method of manufacturing a semiconductor device having a first region in which a plurality of first MISFETs are formed and a second region in which a plurality of second MISFETs are formed,

the method comprising the steps of:

(a) forming a plurality of trenches in a semiconductor layer in the first region and the second region;

(b) forming a first insulator inside each of the plurality of trenches in the first region and the second region;

(c) forming a second insulator having a thickness smaller than that of the first insulator inside each of a part of the plurality of trenches in the first region and the second region; and

(d) burying a gate electrode inside each of the plurality of trenches in the first region and the second region interposing the first insulator or the second insulator after the step (b) and the step (c),

wherein, among the plurality of trenches in the first region, inside the first outermost trench that is the closest to the second region, the first insulator is formed to an upper part and a lower part of the first outermost trench in the step (b), and

inside each of the plurality of trenched in the first region other than the first outermost trench, the first insulator is formed to each of the lower parts of the plurality of trenches in the step (b), and the second insulator is formed to each of the upper parts of the plurality of trenches in the step (c).

19. The method of manufacturing a semiconductor device according to claim 18,

wherein, among the plurality of trenches in the second region, inside the second outermost trench that is the closest to the first region, the first insulator is formed to an upper part and a lower part of the second outermost trench in the step (b), and

inside each of the plurality of trenched in the second region other than the second outermost trench, the first insulator is formed to each of the lower parts of the plurality of trenches in the step (b), and the second insulator is formed to each of the upper parts of the plurality of trenches in the step (c).

20. The method of manufacturing a semiconductor device according to claim 19,

wherein the first insulator is not formed inside each of the first outermost trench and the second outermost trench.