SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20190326434A1
• Filed: 04/04/2019
• Published: 10/24/2019
• Est. Priority Date: 04/24/2018
• Status: Active Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: SEKIKAWA, Hiroaki, MORI, Takahiro, ISHII, Yuji
• Granted Patent: US 11,329,152 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of manufacturing a semiconductor device of one embodiment includes the steps of: forming a drift region in a first surface of a semiconductor substrate; forming a body region having a first portion disposed in the first surface, and a second portion disposed in the first surface so as to surround the first portion and the drift region; forming a hard mask, having an opening over the drift region, in the first surface; forming a reverse conductivity region in the first surface by ion implantation using the hard mask; forming a trench in the first surface by anisotropic etching using the hard mask; and embedding an isolation film in the trench. The ion implantation is performed obliquely to the first surface such that ions are implanted below a first edge part, which is located on a first portion side of the opening, of the hard mask.

Claims

1-17. -17. (canceled)

18. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming a first region in a first surface of a semiconductor substrate, a second region having a first portion in the first surface and a second portion in the first surface so as to surround the first portion and the first region;

forming a mask film over the first surface, the mask film having an opening over the first region;

forming a reverse conductivity region in the first surface by ion implantation using the mask film;

forming a trench in the first surface by anisotropic etching using the mask film;

embedding an insulating film in the trench;

forming a source region in the first surface so as to be surrounded by the second region; and

forming a drain region in the first surface so as to be surrounded by the first region, and

wherein the second region and the reverse conductivity region have a conductivity type opposite to a conductivity type of the source region, the drain region and the first region.

19. The method according to claim 18, wherein the ion implantation is performed obliquely to the first surface such that ions are implanted below a first edge part of the mask film, the first edge part being located on a side of the opening, the side being close to the first portion.

20. The method according to claim 18, further comprising, before the forming the reverse conductivity region, forming a photoresist so as to cover a second edge part of the mask film, the second edge part being located opposite to the first edge part with respect to the opening,

wherein the reverse conductivity region surrounds the drain region in plan view,

wherein the source region surrounds the reverse conductivity region in plan view,

wherein the ion implantation is performed through first ion implantation along a first direction in plan view, second ion implantation along a second direction orthogonal to the first direction in plan view, third ion implantation along a third direction opposite to the first direction in plan view, and fourth ion implantation along a fourth direction opposite to the second direction in plan view, and

wherein the first direction, the second direction, the third direction, and the fourth direction are each different from an extending direction of the drain region in plan view.

21. The method according to claim 18, wherein the forming the reverse conductivity region is performed before the forming the trench.

22. The method according to claim 18, wherein the forming the reverse conductivity region is performed after the forming the insulating film.

23. The method according to claim 18, wherein the forming the reverse conductivity region is performed after the forming the trench and before the embedding the insulating film.

24. The method according to claim 18, wherein a width of the reverse conductivity region in a channel length direction is smaller than a depth of the isolation film.

25. The method according to claim 24, wherein the width is 0.5 times or more than the depth.

26. The method according to claim 18, wherein the mask film is a hard mask.

27. The method according to claim 18,

wherein the first region is a drift region, and

wherein the second region is the body region.

28. A method of manufacturing a semiconductor device, the method comprising the steps of:

providing a semiconductor substrate having a first surface;

thrilling a first region in the first surface;

forming a second region having a first portion disposed in the first surface, and a second portion disposed in the first surface so as to surround the first portion and the first region;

forming a mask film over the first surface, the mask film having an opening over the first region;

forming a trench in the first surface by anisotropic etching using the mask film;

forming a reverse conductivity region in a side surface and a bottom surface of the trench by ion implantation using the mask film;

embedding an isolation film in the trench;

forming a source region in the first surface so as to be surrounded by the second region; and

forming a drain region in the first surface so as to be surrounded by the first region, and

wherein the second region and the reverse conductivity region have a conductivity type opposite to a conductivity type of the source region, the drain region, and the first region.

29. The method according to claim 28, wherein the ion implantation is performed obliquely to the first surface such that ions are implanted into the side surface and the bottom surface.

30. The method according to claim 28, wherein the mask film is a hard mask.

31. The method according to claim 28,

wherein the first region is the drift region, and

wherein the second region is the body region.

32. A method of manufacturing a semiconductor device, the method comprising the steps of:

providing a semiconductor substrate having a first surface;

forming a third region and a forth region in the first surface;

forming a fifth region having a first portion disposed in the first surface and a second portion disposed in the first surface so as to surround the first portion and the third region, and a sixth region having a third portion disposed in the first surface and a fourth portion disposed in the first surface so as to surround the third portion and the forth region;

forming a mask film over the first surface, the mask film having a first opening over the third region and a second opening over the forth region;

forming a first trench and a second trench in the first surface by anisotropic etching using the mask film;

forming a photoresist;

forming a first reverse conductivity region below a first edge part of the mask film, the first edge part being located on a side of the first opening, the side being close to the first portion, and forming a second reverse conductivity region in a bottom surface and a side surface of the second trench, by ion implantation using the mask film and the photoresist;

embedding a first isolation film in the first trench, and embedding a second isolation film in the second trench;

forming a first source region in the first surface so as to be surrounded by the fifth region, and forming a second source region in the first surface so as to be surrounded by the sixth region; and

forming a first drain region in the first surface so as to be surrounded by the third region, and forming a second drain region in the first surface so as to be surrounded by the forth region,

wherein the photoresist is formed so as to cover a second edge part of the mask film, the second edge part being located opposite to the first edge part with respect to the first opening; and

wherein the fifth region, the sixth region, the first reverse conductivity region, and the second reverse conductivity region have a conductivity type opposite to a conductivity type of the first source region, the second source region, the first drain region, the second drain region, the third region, and the forth region.

33. The method according to claim 32, wherein the ion implantation is performed obliquely to the first surface such that ions are implanted below the first edge part and implanted into the side surface and the bottom surface.

34. The method according to claim 32, wherein the mask film is a hard mask.

35. The method according to claim 32,

wherein the third region is a first drift region,

wherein the forth region is a second drift region,

wherein the fifth region is a first body region, and

wherein the sixth region is a second body region.