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VERTICAL FIELD-EFFECT TRANSISTOR INCLUDING A FIN HAVING SIDEWALLS WITH A TAPERED BOTTOM PROFILE

  • US 20190326435A1
  • Filed: 04/18/2018
  • Published: 10/24/2019
  • Est. Priority Date: 04/18/2018
  • Status: Active Grant
First Claim
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1. A method of forming a semiconductor structure comprising:

  • forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin comprises a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion;

    forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile; and

    forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin;

    wherein the at least one fin comprises a channel for a vertical field-effect transistor; and

    further comprising forming an oxide layer disposed over the top surface of the substrate surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile, the bottom source/drain region being disposed over a top surface of the oxide layer;

    wherein forming the at least one fin comprises;

    patterning a hard mask layer over a portion of the substrate; and

    etching portions of the substrate exposed by the hard mask layer to form the at least one fin; and

    wherein forming the oxide layer comprises;

    filling an oxide over the top surface of the substrate;

    planarizing the oxide with a top surface of the hard mask layer; and

    recessing the oxide to reveal at least part of the first portion of the sidewalls of the at least one fin having the tapered profile.

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