SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

• US 20190326437A1
• Filed: 07/01/2019
• Published: 10/24/2019
• Est. Priority Date: 03/25/2016
• Status: Active Grant

• Current Assignee: National Taiwan University (Government of The Republic of China), Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: National Taiwan University (Government of The Republic of China), Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LAN, Huang-Siang, LIU, CheeWee, LIU, Chi-Wen, HUANG, Shih-Hsien, WONG, I-Hsieh, YEH, Hung-Yu, TSAI, Chung-En
• Granted Patent: US 11,631,768 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02535 including tin
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 10¹⁹ atoms cm⁻³ or less of a dopant, and a portion of the fin under the gate structure is a channel region.

Claims

1. A semiconductor device comprising:

a fin extending along a first direction over a substrate;

a gate structure extending in a second direction overlying the fin,

wherein the gate structure comprises;

a gate dielectric layer overlying the fin;

a gate electrode overlying the gate dielectric layer; and

insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction,

wherein a portion of the fin under the gate structure is a channel region;

a first source/drain region in the fin in a first region adjacent a first side of the gate electrode structure;

a second source/drain region in the fin in a second region adjacent a second side of the gate electrode structure opposing the first side of the gate electrode structure,

a stressor layer between the channel region and the semiconductor substrate, and between the first source/drain region and the second source/drain region;

wherein the stressor layer comprises GeSn or SiGeSn containing about 10¹⁹ atoms cm<sup>−

3</sup> or less of a dopant; and

a strain relaxed buffer layer between the stressor layer and the semiconductor substrate.

2. The semiconductor device of claim 1, wherein the stressor layer comprises undoped GeSn or undoped SiGeSn.

3. The semiconductor device of claim 1, wherein the channel region comprises Ge, SiGe, GeSn, or SiGeSn.

4. The semiconductor device of claim 1, wherein the first and second source/drain regions comprise Ge or SiGe.

5. The semiconductor device of claim 1, wherein the first source/drain region and the second source/drain region comprise a dopant at a concentration of greater than 10²⁰ atoms cm⁻

3.

6. The semiconductor device of claim 1, wherein the strain relaxed buffer layer comprises Ge, SiGe, SiGeSn, or GeSn.

7. A method for manufacturing a semiconductor device, comprising:

forming one or more fins extending in a first direction over a substrate,

wherein the one or more fins include at least one first region along the first direction and second regions on either side of each first region along the first direction, and the first region is a channel region;

forming a gate structure extending along a second direction overlying the first region of the fins,

wherein the gate structure comprises;

a gate dielectric layer overlying the fin;

a gate electrode overlying the gate dielectric layer; and

a pair of insulating gate sidewalls formed on opposing lateral surfaces of the gate electrode extending along the second direction;

forming a stressor layer on the semiconductor substrate; and

forming source/drain regions in the second regions of the fin,

wherein the stressor layer is located between the source/drain regions and between the semiconductor substrate and the channel region, and

the stressor layer comprises GeSn or SiGeSn containing about 10¹⁹ atoms cm<sup>−

3</sup> or less of a dopant.

8. The method according to claim 7, wherein the gate structure comprises a dummy gate electrode and dummy gate dielectric layer, and the method further comprises:

removing the dummy gate electrode and dummy gate dielectric layer to form a gate space after forming the source/drain regions;

forming a high-k dielectric layer in the gate space; and

forming a metal gate electrode overlying the high-k dielectric layer in the gate space.

9. The method according to claim 7, further comprising forming a strain relaxed buffer layer on the semiconductor substrate before forming the one or more fins.

10. The method according to claim 7, further comprising:

forming a strain relaxed buffer layer on the semiconductor substrate; and

forming the stressor on the strain relaxed buffer layer before forming the gate structure.

11. The method according to claim 10, further comprising forming a channel region over the stressor layer before forming the gate structure.

12. The method according to claim 11, wherein the gate structure comprises a dummy gate electrode and dummy gate dielectric layer, and the method further comprises:

patterning the dummy gate electrode and dummy gate dielectric layer to provide a dummy gate structure; and

etching the channel region and the stressor layer over the second region of the fins to expose the strain relaxed buffer layer before forming the source/drain regions.

13. The method according to claim 7, wherein the stressor layer comprises undoped GeSn or undoped SiGeSn.

14. The method according to claim 7, wherein the strain relaxed buffer layer comprises Ge, SiGe, SiGeSn, or GeSn.

15. A complementary metal-oxide-semiconductor (CMOS) device comprising:

a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) formed on a semiconductor substrate,

the PFET and the NFET each comprise;

a fin extending along a first direction over a substrate;

a gate structure extending in a second direction overlying the fin,

wherein the gate structure comprises;

a gate dielectric layer overlying the fin;

a gate electrode overlying the gate dielectric layer; and

insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction,

wherein a portion of the fin under the gate structure is a channel region;

a source/drain region in the fin in a region adjacent the gate structure,

wherein the source/drain region consists essentially of Ge or SiGe and a first dopant;

a stressor layer below the source/drain,

wherein the stressor layer comprises GeSn or SiGeSn containing about 10¹⁹ atoms cm<sup>−

3</sup> or less of a dopant; and

a strain relaxed buffer layer between the stressor layer and the semiconductor substrate,

wherein the PFET and NFET are spaced apart from each other with an insulating layer therebetween.

16. The semiconductor device of claim 15, wherein the source/drain regions further comprise a dopant at a concentration of greater than 10²⁰ atoms cm⁻

3.

17. The semiconductor device of claim 15, wherein the stressor layer extends below the channel region.

18. The semiconductor device of claim 15, further comprising a passivation layer disposed between the channel region and the gate dielectric layer.

19. The semiconductor device of claim 18, further comprising a pair of source/drain regions adjacent opposing sides of the channel region,

wherein the passivation layer is disposed between the pair of source/drain regions.

20. The semiconductor device of claim 15, further comprising source/drain contacts disposed over the source/drain regions and adjacent to the insulating gate sidewalls.