PHASE-CHANGE MEMORY CELL HAVING A COMPACT STRUCTURE

• US 20190326510A1
• Filed: 06/28/2019
• Published: 10/24/2019
• Est. Priority Date: 06/23/2015
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: BOIVIN, Philippe, JEANNOT, Simon
• Granted Patent: US 11,031,550 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/061 Patterning of the switching material
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/253 having three or more terminals, e.g. transistor-like devices
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8265 on sidewalls of dielectric structures, e.g. mesa or cup type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

Claims

1. A process for fabricating a memory cell, the process comprising:

covering a semiconductor substrate with a first insulating layer;

covering the first insulating layer with an active layer made of a semiconductor material;

forming a first control gate and first and second conduction regions of a first selection transistor;

covering, with a second insulating layer, a lateral flank of the first control gate on the same side as the first conduction region;

producing a first trench through the active layer in the first conduction region, reaching the first insulating layer;

depositing a first layer in the first trench, covering a first lateral flank of the active layer in the trench; and

depositing a second layer in contact with the first layer, wherein one of the first and second layers is made of a variable-resistance material, in which the second layer is made of the variable-resistance material, extends longitudinally in a plane parallel to the surface of the substrate and makes contact with an upper portion of the first layer, the first layer including a first resistor configured to heat the second layer in order to make the second layer change phase between a non-conductive amorphous phase and a conductive crystalline phase.

2. The process according to claim 1, comprising depositing, on a lateral flank of the first layer, a third insulating layer, and etching a second trench in the first layer along the third insulating layer, until the first insulating layer is reached.

3. The process according to claim 2, comprising filling the second trench with a dielectric material that contacts the second layer.

4. The process according to claim 1, further comprising:

forming a second control gate and a third conduction terminal of a second selection transistor; and

covering, with the second insulating layer, a lateral flank of the second control gate.

5. The process according to claim 4, wherein producing the first trench includes dividing the first conduction region into first and second conductive sub-regions, the first conductive sub-region being a source or drain region of the first selection transistor and the second conductive sub-region being a source or drain region of the second selection transistor.

6. The process according to claim 5, in which depositing the first layer in the first trench includes covering a bottom and a second lateral flank of the active layer in the trench.

7. The process according to claim 6, comprising:

forming first and second insulating spacers on first and second lateral flanks of the first layer, respectively, the first and second insulating spacers leaving exposed a central portion of the first layer; and

etching a second trench through the central portion of the first layer while the first and second lateral flanks of the first layer are protected by the first and second insulating spacers, respectively.

8. The process according to claim 7, wherein the first resistor contacts the second layer at a first contact portion and etching the second trench includes dividing the first layer into the first resistor and a second resistor, the second resistor contacting the second conductive sub-region and a second contact portion of the second layer, the first and second contact portions being spaced apart from each other.

9. A memory cell comprising:

a semiconductor substrate;

a first insulating layer covering a surface of the semiconductor substrate;

a semiconductor active layer covering the first insulating layer;

a control gate of a selection transistor, the control gate being formed on the active layer and having a lateral flank;

a second insulating layer covering the lateral flank of the control gate;

first and second conduction regions of the selection transistor, the first and second conduction regions being formed in the active layer;

a trench formed through the active layer, the trench being defined on a first side by a first lateral flank of the active layer and reaching the first insulating layer;

a variable-resistance element electrically coupled to first conduction terminal of the selection transistor and including;

a first layer of resistive material covering the first lateral flank of the active layer in the trench, and

a second layer contacting the first layer, wherein second layer is made of a variable-resistance material.

10. The memory cell according to claim 9, in which the second layer contacts an upper portion of the first layer, and extends longitudinally in a plane parallel to the surface of the substrate.

11. The memory cell according to claim 10, comprising a dielectric trench isolation formed under the second layer and in the trench and covering a lateral flank of the first layer.

12. The memory cell according to claim 9, wherein:

the second insulating layer extends above the control gate;

the first layer extends upwardly from the trench along the second insulating layer and reaches a top surface of the second insulating layer; and

the second layer is positioned above the second insulating layer.

13. A memory comprising:

a plurality of wordlines;

a plurality of bit lines;

a plurality of source lines;

a semiconductor substrate

a first insulating layer covering a surface of the semiconductor substrate;

a semiconductor active layer covering the first insulating layer;

a first memory cell including;

a control gate of a first selection transistor, the control gate being formed on the active layer and having a lateral flank;

a second insulating layer covering the lateral flank of the control gate;

first and second conduction regions of the first selection transistor, the first and second conduction regions being formed in the active layer; and

a variable-resistance element electrically coupled to first conduction region of the first selection transistor and including;

a first layer of resistive material extending in the active layer and contacting the first conduction region, and

a second layer contacting the first layer, wherein second layer is made of a variable-resistance material.

14. The memory according to claim 13, wherein the first layer extends in a trench through the active layer, covers a first lateral flank of the active layer, and contacts a first contact portion of the second layer, the memory further comprising a second memory cell that includes a third layer of resistive material extending in the trench, covering a second lateral flank of the active layer, and contacts a second contact portion of the second layer.

15. The memory according to claim 14, wherein the second memory cell includes a second selection transistor that includes:

a control gate formed on the active layer and having a lateral flank;

a third insulating layer covering the lateral flank of the control gate of the second selection transistor;

first and second conduction regions formed in the active layer, wherein the third layer contacts the first conduction region of the second selection transistor.

16. The memory according to claim 15, wherein the second conduction terminal of the first selection transistor is shared with a third memory cell of the memory and the second conduction terminal of the second selection transistor is shared with a fourth memory cell of the memory.

17. The memory according to claim 14, further comprising a dielectric trench isolation formed under the second layer and insulating the first layer from the third layer in the trench.

18. The memory according to claim 17, wherein the second layer extends longitudinally in a plane parallel to the surface of the substrate and makes contact with upper portions of the first and third layers, the first layer being configured to heat a first contact portion of the second layer and make the first contact portion of the second layer change phase between a non-conductive amorphous phase and a conductive crystalline phase, and the third layer being configured to heat a second contact portion of the second layer and make the second contact portion of the second layer change phase between the non-conductive amorphous phase and the conductive crystalline phase.

19. The memory according to claim 13, wherein the second layer extends longitudinally in a plane parallel to the surface of the substrate and makes contact with an upper portion of the first layer, the first layer being configured to heat a contact portion of the second layer and make the contact portion of the second layer change phase between a non-conductive amorphous phase and a conductive crystalline phase.

20. The memory cell according to claim 13, wherein:

the second insulating layer extends above the control gate of the first selection transistor;

the first layer extends upwardly from the first conduction region along the second insulating layer and reaches a top surface of the second insulating layer; and

the second layer is positioned on the second insulating layer.