ELECTROSTATIC DISCHARGE CIRCUIT

• US 20190326749A1
• Filed: 02/21/2019
• Published: 10/24/2019
• Est. Priority Date: 04/18/2018
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: LAI, Chih-Wei, TING, Yun-Jen, WU, Yi-Han, LIN, Kun-Hsin, HSU, Hsin-Kun
• Granted Patent: US 10,944,258 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

An ESD circuit is connected to a power pad and a first node. The ESD circuit includes a RC circuit and a first ESD current path. The RC circuit is connected between the power pad and the first node. The RC circuit is capable of providing a first control voltage and a second control voltage. The first ESD current path is connected between the power pad and the first node. When the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.

Claims

1. An electrostatic discharge (ESD) circuit connected to a power pad and a first node, the ESD circuit comprising:

a RC circuit connected between the power pad and the first node, wherein the RC circuit is capable of providing a first control voltage and a second control voltage; and

a first ESD current path connected between the power pad and the first node, wherein when the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.

2. The ESD circuit as claimed in claim 1, further comprising:

a first P-type transistor, wherein a first drain/source terminal and a body terminal of the first P-type transistor are connected to the power pad, a gate terminal of the first P-type transistor receives the first control voltage, and a second drain/source terminal of the first P-type transistor is connected to a second node; and

a first N-type transistor, wherein a first drain/source terminal of the first N-type transistor is connected to the second node, a gate terminal of the first N-type transistor receives the second control voltage, and a second drain/source terminal and a body terminal of the first N-type transistor are connected to the first node.

3. The ESD circuit as claimed in claim 2, wherein the first ESD current path is defined by the first drain/source terminal of the first P-type transistor, a channel region of the first P-type transistor, the second drain/source terminal of the first P-type transistor, the first drain/source terminal of the first N-type transistor, a channel region of the first N-type transistor, the second drain/source terminal of the first N-type transistor.

4. The ESD circuit as claimed in claim 2, wherein the first P-type transistor comprises a first parasitic diode, an anode terminal of the first parasitic diode is connected to the second drain/source terminal of the first P-type transistor, and a cathode terminal of the first parasitic diode is connected to the first drain/source terminal of the first P-type transistor, and wherein the first N-type transistor comprises a second parasitic diode, an anode terminal of the second parasitic diode is connected to the second drain/source terminal of the first N-type transistor, and a cathode terminal of the second parasitic diode is connected to the first drain/source terminal of the first N-type transistor.

5. The ESD circuit as claimed in claim 4, wherein a second ESD current path is defined by the second drain/source terminal of the first N-type transistor, the second parasitic diode, the first drain/source terminal of the first N-type transistor, the second drain/source terminal of the first P-type transistor, the first parasitic diode and the first drain/source terminal of the first P-type transistor.

6. The ESD circuit as claimed in claim 1, wherein when the power pad receives a negative ESD zap, a second ESD current path is turned on, so that the ESD current flows from the first node to the power pad through the second ESD current path.

7. The ESD circuit as claimed in claim 1, wherein the RC circuit comprises:

a first resistor, wherein a first terminal of the first resistor is connected to the power pad, and a second terminal of the first resistor is connected to a third node;

a second resistor, wherein a first terminal of the second resistor is connected to a fourth node, and a second terminal of the second resistor is connected to the first node; and

a capacitor bank, wherein a first terminal of the capacitor bank is connected to the third node, and a second terminal of the capacitor bank is connected to the fourth node,

wherein the third node outputs the first control voltage, and the fourth node outputs the second control voltage.

8. The ESD circuit as claimed in claim 7, wherein the capacitor bank includes at least one capacitor.

9. The ESD circuit as claimed in claim 8, wherein the first resistor and the second resistor are polysilicon resistors or the at least one capacitor is a Metal-Insulator-Metal capacitor.

10. The ESD circuit as claimed in claim 7, wherein a first drain/source terminal and a body terminal of a second P-type transistor are connected to each other and served as the first terminal of the first resistor, and a second drain/source terminal and a gate terminal of the second P-type transistor are connected to each other and served as the second terminal of the first resistor, wherein a first drain/source terminal and a body terminal of a third P-type transistor are connected to each other and served as the first terminal of the second resistor, and a second drain/source terminal and a gate terminal of the third P-type transistor are connected to each other and served as the second terminal of the second resistor.

11. The ESD circuit as claimed in claim 7, wherein the capacitor bank comprises:

a first capacitor, wherein a first terminal of the first capacitor is connected to the third node, and a second terminal of the first capacitor is connected to a fifth node; and

a second capacitor, wherein a first terminal of the second capacitor is connected to the fifth node, and a second terminal of the second capacitor is connected to the fourth node.

12. The ESD circuit as claimed in claim 11, wherein a first drain/source terminal, a second drain/source terminal and a body terminal of a fourth P-type transistor are connected to each other and served as the first terminal of the first capacitor, and a gate terminal of the fourth P-type transistor is served as the second terminal of the first capacitor, wherein a first drain/source terminal, a second drain/source terminal and a body terminal of a fifth P-type transistor are connected to each other and served as the first terminal of the second capacitor, and a gate terminal of the fifth P-type transistor is served as the second terminal of the second capacitor.