WIDE RANGE INPUT VOLTAGE DIFFERENTIAL RECEIVER

• US 20190326896A1
• Filed: 04/29/2019
• Published: 10/24/2019
• Est. Priority Date: 09/27/2017
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Nguyen, Huy M., Lee, Seong Hoon
• Granted Patent: US 10,566,963 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A method and apparatus for receiving reduced voltage swing signals is disclosed. A first amplifier may generate a first intermediate signal based on a difference between voltage levels of a first and second input signals, and a second amplifier may generate a second intermediate signal based on a difference in the voltage levels between the second and first input signals. A regenerative amplifier may increase a difference in the voltage level of the first and second intermediate signals using regenerative feedback and the voltage levels of the first and second input signals. A latch circuit may generate first and second output signals using the first and second intermediate signals.

Claims

1-20. -20. (canceled)

21. An apparatus, comprising:

a first amplifier circuit configured to amplify a difference in respective voltage levels of a first input signal and a second input signal to generate a first difference signal;

a second amplifier circuit configured to amplify the difference in the respective voltage levels of the first input signal and the second input signal to generate a second difference signal that has an opposite polarity of the first difference signal;

a regenerative feedback circuit configured to increase a difference in respective voltage levels of the first difference signal and the second difference signal; and

a latch circuit configured to capture a logical state using the first difference signal and the second difference signal.

22. The apparatus of claim 21, further comprising a duty cycle correction circuit configured to change a duty cycle of an output signal of the latch circuit to generate a corrected signal.

23. The apparatus of claim 22, wherein the duty cycle correction circuit is further configured to change, using at least one control signal, the duty cycle of the output signal.

24. The apparatus of claim 22, wherein the duty cycle correction circuit is further configured to decouple from an output circuit node in response to an assertion of a control signal.

25. The apparatus of claim 21, wherein the regenerative feedback circuit is further configured to initialize the first difference signal and the second difference signal using at least one enable signal.

26. The apparatus of claim 21, wherein the first amplifier circuit includes a local power supply node, and wherein the first amplifier circuit is further configured to decouple the local power supply node from a global power supply node using an enable signal.

27. A method, comprising:

transmitting, by a first circuit, a first signal and a second signal via a communication bus;

receiving, by a second circuit, the first signal and the second signal via the communication bus;

generating, by the second circuit, a first difference signal using the first signal and the second signal, wherein the first difference signal has a first polarity;

generating by the second circuit, a second difference signal using the first signal and the second signal, wherein the second difference signal has a second polarity different from the first polarity;

increasing, by the second circuit, a voltage difference between the first difference signal and the second difference signal; and

capturing, by the second circuit, a logic state differentially encoded by the first difference signal and the second difference signal.

28. The method of claim 27, further comprising, generating, by the second circuit, a first output signal and a second output signal using the logic state.

29. The method of claim 28, further comprising, changing, by the second circuit, a duty cycle of at least one of the first output signal and the second output signal to generate a corrected signal.

30. The method of claim 29, further comprising, determining, by the second circuit, an amount of duty cycle correct using one or more control signals.

31. The method of claim 27, further comprising, initializing, by the second circuit, the first difference signal and the second difference signal using at least one enable signal.

32. The method of claim 27, wherein the second circuit includes a driver circuit coupled to an output circuit node, and further comprising, decoupling, by the second circuit, the driver circuit from the output circuit node.

33. The method of claim 27, wherein the second circuit includes a local power supply node, and further comprising, decoupling, by the second circuit, the local power supply node from a global power supply node using an enable signal.

34. An apparatus, comprising:

a first circuit block including a transmitter circuit configured to via a communication bus;

a second circuit block including a receiver circuit configured to;

receive a first signal and a second signal via the communication bus;

generate a first difference signal using the first signal and the second signal, wherein the first difference signal has a first polarity;

generate a second difference signal using the first signal and the second signal, wherein the second difference signal has a second polarity different from the first polarity;

increase a voltage difference between the first difference signal and the second difference signal; and

capture a logic state differentially encoded by the first difference signal and the second difference signal.

35. The apparatus of claim 34, wherein the receiver circuit is further configured to generate a first output signal and a second output signal using the logic state.

36. The apparatus of claim 35, wherein the receiver circuit is further configured to change a duty cycle of at least one of the first output signal and the second output signal to generate a corrected signal.

37. The apparatus of claim 36, wherein the receiver circuit is further configured to determine an amount of duty cycle correct using one or more control signals.

38. The apparatus of claim 34, wherein the receiver circuit is further configured to initialize, using at least one enable signal, the first difference signal and the second difference signal.

39. The apparatus of claim 34, wherein the receiver circuit includes a driver circuit coupled to an output circuit node, and wherein the receiver circuit is further configured to decouple the driver circuit from the output circuit node.

40. The apparatus of claim 34, wherein the receiver circuit includes a local power supply node, and wherein the receiver circuit is further configured to decouple, decoupling the local power supply node from a global power supply node using an enable signal.