ANALOG TO DIGITAL CONVERTOR (ADC) USING A COMMON INPUT STAGE AND MULTIPLE PARALLEL COMPARATORS
First Claim
Patent Images
1. An apparatus comprising:
- a common input stage coupled to a first power supply node;
a first switch coupled to the common input stage, wherein the first switch is controllable by a first clock;
a load device coupled in series with the first switch;
a second switch coupled in series with the load and a ground supply node, wherein the second switch is controllable by the first clock;
a third switch coupled to a second power supply node, wherein the third switch is controllable by a reset; and
a circuitry coupled to the third switch and the second switch.
0 Assignments
0 Petitions
Accused Products
Abstract
An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
-
Citations
20 Claims
-
1. An apparatus comprising:
-
a common input stage coupled to a first power supply node; a first switch coupled to the common input stage, wherein the first switch is controllable by a first clock; a load device coupled in series with the first switch; a second switch coupled in series with the load and a ground supply node, wherein the second switch is controllable by the first clock; a third switch coupled to a second power supply node, wherein the third switch is controllable by a reset; and a circuitry coupled to the third switch and the second switch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. An apparatus comprising:
-
a common input stage coupled to a first power supply node; and a plurality of comparison and latch circuitries, wherein at least one of the comparison and latch circuitries of the plurality is coupled to the common input stage, wherein an output of an individual one of the plurality of comparison and latch circuitries is to sequentially trigger initiation of a comparison and latch operation by a subsequent comparison and latch circuitry of the plurality of comparison and latch circuitries, wherein the individual one of the plurality of comparison and latch circuitries comprises; a first switch coupled to the common input stage, wherein the first switch is controllable by a first clock; a load device coupled in series with the first switch; a second switch coupled in series with the load and a ground supply node, wherein the second switch is controllable by the first clock; a third switch coupled to a second power supply node, wherein the third switch is controllable by a reset; and a circuitry coupled to the third switch and the second switch. - View Dependent Claims (15, 16)
-
-
17. A system comprising:
-
a memory to store instructions; a processor coupled to the memory, wherein the processor is to execute the instructions; and an antenna communicatively coupled to the processor, wherein the processor includes an analog-to-digital converter (ADC) which comprises; a common input stage coupled to a first power supply node; a first switch coupled to the common input stage, wherein the first switch is controllable by a first clock; a load device coupled in series with the first switch; a second switch coupled in series with the load and a ground supply node, wherein the second switch is controllable by the first clock; a third switch coupled to a second power supply node, wherein the third switch is controllable by a reset; and a circuitry coupled to the third switch and the second switch. - View Dependent Claims (18, 19, 20)
-
Specification