APPARATUS FOR OVERLOAD RECOVERY OF AN INTEGRATOR IN A SIGMA-DELTA MODULATOR

• US 20190326925A1
• Filed: 06/28/2019
• Published: 10/24/2019
• Est. Priority Date: 06/25/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: KAUFFMAN, John G., DUFRENE, Krzysztof
• Granted Patent: US 10,749,544 B2
• Time in Patent Office: Days
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/06 Continuously compensating for, or preventing, undesired influence of physical parameters periodically, e.g. by using stored correction values, H03M1/10
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/10 Calibration or testing
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter
• CPC Class Codes: H03M 3/30 Delta-sigma modulation
• CPC Class Codes: H03M 3/356 Offset or drift compensation removal of offset already present on the analogue input signal H03M3/494
• CPC Class Codes: H03M 3/386 over the full range of the converter, e.g. for correcting differential non-linearity
• CPC Class Codes: H03M 3/424 the quantiser being a multiple bit one
• CPC Class Codes: H03M 3/444 using non-linear elements, e.g. limiters
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
• CPC Class Codes: H03M 3/464 Details of the digital/analogue conversion in the feedback path

Abstract

Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

Claims

1. An apparatus comprising:

a first integrator to receive an input and to generate a first output;

a second integrator to receive the first output or a version of the first output and to generate a second output;

an analog-to-digital converter (ADC) to quantize the second output into a digital representation;

logic to detect whether the second output is saturated at a first voltage level or a second voltage level for at least two consecutive cycles; and

circuitry to adjust current at the first integrator, without bypassing the first integrator, responsive to the logic detecting that the second output is saturated at a first voltage level or a second voltage level for at least two consecutive cycles.

2. The apparatus of claim 1 comprising:

a digital-to-analog converter (DAC) coupled to an input of the first integrator.

3. The apparatus of claim 1, wherein the logic comprises registers.

4. The apparatus of claim 1, wherein the first and second integrators are differential integrators.

5. The apparatus of claim 1 comprising:

a first digital-to-analog converter (DAC) coupled to an input of the first integrator; and

a second DAC coupled to the output of the first integrator.

6. The apparatus of claim 5, wherein the second DAC to provide a second analog signal which is combined with the first output from the first integrator, and wherein the second DAC to adjust a signal attribute of the second output according to the digital representation.

7. The apparatus of claim 1, wherein the ADC comprises a successive approximation (SAR) quantizer.

8. The apparatus of claim 1, wherein the ADC comprises a sigma-delta converter.

9. The apparatus of claim 1, wherein the first voltage level is substantially a power supply voltage level, and wherein the second voltage level is substantially a ground voltage level.

10. A multi-order sigma-delta (SD) analog-to-digital converter (ADC), comprising:

‘

N’

number of orders including a first integrator and a second integrator, wherein the first integrator is to receive an input and to generate a first output, and wherein the second integrator is to receive the first output or a version of the first output and to generate a second output;

a quantizer to quantize the second output into a digital representation

logic to detect whether the second output is saturated at a first voltage level or a second voltage level for at least two consecutive cycles; and

circuitry to reduce current at the output of the first integrator while maintaining the N order, responsive to the logic detecting that the second output is saturated at a first voltage level or a second voltage level for at least two consecutive cycles.

11. The multi-order SD ADC of claim 10, wherein the first voltage level is substantially a power supply voltage level, and wherein the second voltage level is substantially a ground voltage level.

12. The multi-order SD ADC of claim 10, wherein the quantizer comprises a successive approximation (SAR) quantizer.

13. The multi-order SD ADC of claim 10, wherein the logic comprises registers.

14. The multi-order SD ADC of claim 10, wherein the first and second integrators are differential integrators.

15. An apparatus comprising:

a first integrator to receive an input and to generate a first output;

a second integrator to receive the first output or a version of the first output and to generate a second output;

an analog-to-digital converter (ADC) to quantize the second output into a digital representation;

logic to detect whether the second output is stuck at a level for at least two consecutive cycles; and

circuitry to adjust current at the first integrator responsive to the logic detecting that the second output is stuck at the level for at least two consecutive cycles.

16. The apparatus of claim 15 comprising:

a digital-to-analog converter (DAC) coupled to an input of the first integrator.

17. The apparatus of claim 15, wherein the logic comprises registers.

18. The apparatus of claim 15, wherein the first and second integrators are differential integrators.

19. The apparatus of claim 15 comprising:

a first digital-to-analog converter (DAC) coupled to an input of the first integrator; and

a second DAC coupled to the output of the first integrator.

20. The apparatus of claim 19, wherein the second DAC to provide a second analog signal which is combined with the first output from the first integrator, and wherein the second DAC to adjust a signal attribute of the second output according to the digital representation.

21. The apparatus of claim 15, wherein the ADC comprises a successive approximation (SAR) quantizer.

22. An apparatus comprising:

an N-order loop filter having at least two integrators;

an analog-to-digital converter (ADC) to quantize an output of the N-order loop filter into a digital representation;

logic to detect whether the output of the N-order loop filter is saturated at a first voltage level or a second voltage level for at least two consecutive cycles; and

circuitry to adjust current at the output of the N-order loop filter, without bypassing the first integrator, when the logic is to detect whether the saturated at the first voltage level or the second voltage level for the at least two consecutive cycles.

23. The apparatus of claim 22 comprises at least two digital-to-analog converters (DACs) at least one of which is coupled to the ADC.

24. The apparatus of claim 22, wherein the logic comprises registers.

25. The apparatus of claim 22, wherein the two integrators are differential integrators.

26. The apparatus of claim 22, wherein the ADC comprises a successive approximation (SAR) quantizer.

27. The apparatus of claim 22, wherein the ADC comprises a sigma-delta converter.