Method and System of Implementing Security Algorithm and Decryption Algorithm by Using Reconfigurable Processor

• US 20190327089A1
• Filed: 02/07/2019
• Published: 10/24/2019
• Est. Priority Date: 04/19/2018
• Status: Active Application

• Current Assignee: Wuxi Research Institute of Applied Technologies Tsinghua University
• Original Assignee: Wuxi Research Institute of Applied Technologies Tsinghua University
• Inventors: Liu, Leibo, Zhu, Min, Wei, Shaojun
• Granted Patent: US 10,848,306 B2
• Time in Patent Office: Days
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/14 using a plurality of keys or algorithms
• CPC Class Codes: H04L 9/16 the keys or algorithms being changed during operation

Abstract

The present disclosure provides a system and method of implementing a security algorithm using a reconfigurable processor, the method including: determining a plurality of sub-algorithms for constructing the security algorithm; and configuring the reconfigurable processor to implement the security algorithm according to a first configuration information of each sub-algorithm of the plurality of sub-algorithms and a first combination configuration information indicating a combination connection relationship of each of the sub-algorithms. The present disclosure also provides a system and method of implementing a decryption algorithm using a reconfigurable processor. Configuration of the reconfigurable processor according to the present disclosure can enable the security of the security algorithm and the security of the security algorithm implementation process to be ensured, the security risks of the sensitive data management and the risk of side channel attacks can be prevented, and the security is extremely high.

Claims

1. A method of implementing a security algorithm by using a reconfigurable processor, comprising:

determining a plurality of sub-algorithms for constructing the security algorithm; and

configuring the reconfigurable processor to implement the security algorithm according to a first configuration information of each sub-algorithm of the plurality of sub-algorithms and a first combination configuration information indicating a combination connection relationship of each of the sub-algorithms, wherein, the first configuration information includes a configuration information required by the reconfigurable processor to implement each sub-algorithm, and the first combination configuration information includes a configuration information required by the reconfigurable processor to implement the combination connection of the plurality of sub-algorithms;

the determining the plurality of sub-algorithms for constructing the security algorithm, comprises,

computing a plurality of index values according to a dynamically changed signal source; and

determining the plurality of sub-algorithms for constructing the security algorithm according to the plurality of index values.

3. The method according to claim 1, wherein, the computing the plurality of index values according to the dynamically changed signal source comprises:

computing the plurality of index values according to a feature parameter and a scene parameter of the reconfigurable processor, wherein, the feature parameter includes hardware feature parameter, and the scene parameter includes system time or ambient temperature.

4. The method according to claim 3, wherein, the determining the plurality of sub-algorithms for constructing the security algorithm according to the plurality of index values comprises:

selecting the plurality of sub-algorithms corresponding to the plurality of index values from a first algorithm library according to the plurality of index values, wherein, the first algorithm library includes the first configuration information of N sub-algorithms, where N is greater than a number of sub-algorithms selected this time.

5. The method according to claim 4, wherein, when the first algorithm library is loaded into the reconfigurable processor, the feature parameter of the reconfigurable processor is used to generate identifiers for uniquely representing each of the sub-algorithms in the first algorithm library.

6. The method according to claim 4, wherein, the computing the plurality of index values according to the feature parameter and the scene parameter of the reconfigurable processor comprises:

computing each of the plurality of index values as follows;

computing a first numerical value according to a first preset algorithm based on the feature parameter and the scene parameter; and

dividing the first numerical value by a total number N of the sub-algorithms in the first algorithm library to obtain a corresponding remainder, and using the remainder as an index value.

7. The method according to claim 3, wherein, the computing the plurality of index values according to the feature parameter and the scene parameter of the reconfigurable processor comprises:

computing a second numerical value according to a second preset algorithm based on the feature parameter and the scene parameter;

using the second numerical value as a seed of a random number generator to obtain a random numerical string; and

selecting the plurality of index values from the random numerical string.

8. The method according to claim 1, wherein, when configuring the reconfigurable processor, the plurality of sub-algorithms are connected in an order indicated in the first combination configuration information, and two sub-algorithms connected to each other are not related.

9. The method according to claim 1, wherein, after configuring the reconfigurable processor, the method further comprises:

reconfiguring in real time a key point of a circuit used to implement the security algorithm in the reconfigurable processor; and

/or

adding randomly a delay circuit into a critical path of the circuit used to implement the security algorithm in the reconfigurable processor.

2. (canceled)

10. A method of implementing a decryption algorithm by using a reconfigurable processor, comprising:

determining a plurality of decryption sub-algorithms for decrypting a security algorithm; and

configuring the reconfigurable processor to implement the decryption algorithm according to a second configuration information of each of the plurality of decryption sub-algorithms and a second combination configuration information indicating a combination connection relationship of each of the decryption sub-algorithms, wherein, the second configuration information includes a configuration information required by the reconfigurable processor to implement each decryption sub-algorithm, and the second combination configuration information includes a configuration information required by the reconfigurable processor to implement the combination connection of the plurality of decryption sub-algorithms;

the determining the plurality of decryption sub-algorithms for decrypting the security algorithm, comprises,

determining a plurality of sub-algorithms of the security algorithm according to a header information of a data packet to be decrypted; and

selecting the plurality of decryption sub-algorithms corresponding to the plurality of sub-algorithms of the security algorithm from a second algorithm library according to the plurality of sub-algorithms of the security algorithm.

12. The method according to claim 10, wherein, before the configuring the reconfigurable processor according to the second configuration information of each of the plurality of decryption sub-algorithms and the second combination configuration information indicating the combination connection relationship of each of the decryption sub-algorithms, the method further comprises:

generating the second combination configuration information according to a reverse order of a connection order of the plurality of sub-algorithms in the security algorithm.

11. (canceled)

13. A computer readable storage medium having executable instructions stored thereon that, when executed by a processor, cause the processor to implement a method of implementing a security algorithm by using a reconfigurable processor, comprising:

determining a plurality of sub-algorithms for constructing the security algorithm; and

configuring the reconfigurable processor to implement the security algorithm according to a first configuration information of each sub-algorithm of the plurality of sub-algorithms and a first combination configuration information indicating a combination connection relationship of each of the sub-algorithms, wherein, the first configuration information includes a configuration information required by the reconfigurable processor to implement each sub-algorithm, and the first combination configuration information includes a configuration information required by the reconfigurable processor to implement the combination connection of the plurality of sub-algorithms;

the determining the plurality of sub-algorithms for constructing the security algorithm, comprises,

computing a plurality of index values according to a dynamically changed signal source; and

determining the plurality of sub-algorithms for constructing the security algorithm according to the plurality of index values; and

/or

implement a method of implementing a decryption algorithm by using a reconfigurable processor, comprising;

determining a plurality of decryption sub-algorithms for decrypting a security algorithm; and

configuring the reconfigurable processor to implement the decryption algorithm according to a second configuration information of each of the plurality of decryption sub-algorithms and a second combination configuration information indicating a combination connection relationship of each of the decryption sub-algorithms, wherein, the second configuration information includes a configuration information required by the reconfigurable processor to implement each decryption sub-algorithm, and the second combination configuration information includes a configuration information required by the reconfigurable processor to implement the combination connection of the plurality of decryption sub-algorithms;

the determining the plurality of decryption sub-algorithms for decrypting the security algorithm, comprises,

determining a plurality of sub-algorithms of the security algorithm according to a header information of a data packet to be decrypted; and

selecting the plurality of decryption sub-algorithms corresponding to the plurality of sub-algorithms of the security algorithm from a second algorithm library according to the plurality of sub-algorithms of the security algorithm.