GLOBAL-SHUTTER VERTICALLY INTEGRATED PIXEL WITH HIGH DYNAMIC RANGE

• US 20190327432A1
• Filed: 04/19/2018
• Published: 10/24/2019
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Inventors: Milkov, Mihail, Douence, Vincent
• Granted Patent: US 10,560,646 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

A pixel comprising a pinned photodiode (PPD) which generates a photocurrent I_ph, a transfer gate connected in series between the PPD and a first node, a low-gain select transistor connected between the first node and a second node, a reset transistor connected between the second node and a reset voltage, a capacitance connected between the second node and a first constant potential, and a source-follower transistor whose source, gate and drain are connected to an output node, the first node and a second constant potential, respectively. When properly arranged, a vertically integrated (3D) global-shutter pinned PPD pixel is provided, which uses an overflow integration capacitor and subthreshold conduction of the reset transistor for increased dynamic range. Global shutter operation is achieved by storing the pixel output on sampling capacitors in another semiconductor layer at the end of integration.

Claims

1. A vertically integrated pixel comprising at least two layers, with layer one comprising:

a pinned photodiode (PPD) which generates photocurrent I_ph;

a transfer gate M_tg connected in series between said PPD and a first node, the voltage at said first node being V_fd and the total capacitance on said first node being C_fd, said transfer gate conducting in response to a control signal txb;

a low-gain select transistor M_lg connected between said first node and a second node, said low-gain select transistor conducting in response to a control signal lgb, the voltage at said second node being a voltage V_int;

a reset transistor M_rst connected between said second node and a reset voltage V_rst, said reset transistor conducting in response to a control signal rstb;

a capacitance C_int connected between said second node and a first constant potential; and

a source-follower transistor M_isf whose source, gate and drain are connected to an output node, said first node and a second constant potential, respectively, such that the voltage at said output node follows V_fd when said source-follower transistor is in a conducting state, said output node connected to another layer of said pixel.

2. The pixel of claim 1, wherein a plurality of said pixels are arranged to form a pixel array, said pixel array operating in global shutter mode such that all pixels of said pixel array receive substantially the same control signals rstb, txb and lgb.

3. The pixel of claim 1, said pixel arranged such that:

during a reset phase;

control signal txb is set such that said transfer gate is not conducting;

control signals lgb and rstb are set such that said low-gain select and reset transistors turn on and reset C_fd and C_int to a voltage V_rst; and

the voltage at said output node is written and stored as the “

low gain”

(LG) reset level while said reset transistor is still on or after said reset transistor turns off; and

during an integration phase, which follows said reset phase;

control signal lgb is set such that said low-gain select transistor remains on thereby shorting said first and second nodes;

control signal rstb is set such that said reset transistor remains off either unconditionally or until the charge on C_int and C_fd exceeds a certain level;

charge is collected and stored in said PPD until it exceeds a threshold level Q_t;

if charge exceeds Q_t, M_tg leaks and the overflow charge is collected on C_int and C_fd; and

during a write phase, which follows said integration phase;

control signal lgb is set such that said low-gain select transistor turns off and the voltage at said output node is written and stored as the “

high gain”

(HG) reset level;

control signal txb is pulsed such that the PPD charge is transferred to C_fd after which the voltage at said output node is written and stored as the HG signal level;

control signal lgb is set such that said low-gain select transistor turns on, control signal txb is pulsed thereby combining the charge on PPD, C_int and C_fd, and the voltage at said output node is written and stored as the LG signal level.

4. The pixel of claim 3, wherein said LG reset level is written during said reset phase after said reset transistor turns off when performing correlated double sampling (CDS).

5. The pixel of claim 3, wherein the amount of photocurrent I_ph integrated during said integration phase is Q_int, said pixel providing a HG output and a LG output such that:

said HG output is equal to the difference between said HG signal level and said HG reset level, said HG output being linear and inversely proportional to C_fd if Q_int is less than a first threshold;

said LG output is equal to said LG signal level or to the difference between said LG signal level and said LG reset level, said LG output being linear and inversely proportional to (C_int+C_fd) if Q_int is less than a second threshold.

6. The pixel of claim 5, wherein said LG output is logarithmically dependent on said photocurrent I_ph if Q_int is equal to or greater than said second threshold.

7. The pixel of claim 5, further comprising circuitry that produces a combined pixel output,

said combined pixel output being proportional to said HG output if said HG output is not saturated, and

said combined pixel output being proportional to said LG output if said HG output is saturated.

8. The pixel of claim 3, wherein said pixel has an associated supply voltage V_dd and said reset transistor M_rst is a PMOS FET, said pixel further arranged such that:

during said integration phase;

said reset transistor gate voltage is at a voltage V_{hi_rstb}<

V_dd;

if charge exceeds said threshold level Q_t, the voltage at said second node V_int is given by;

9. The pixel of claim 3, wherein said reset transistor M_rst is a NMOS FET, said pixel further arranged such that:

during said integration phase;

said reset transistor gate voltage is at a voltage V_{lo_rst}>

0;

if charge exceeds said threshold level Q_t, the voltage at said second node V_int is given by;

10. The pixel of claim 1, wherein said capacitance C_fd comprises the sum of the junction capacitances of transistors M_lg and M_tg, the gate capacitance of transistor M_isf, and the parasitic capacitance at said first node.

11. The pixel of claim 1, wherein said capacitance C_int comprises a metal-insulator-metal (MIM) capacitor.

12. The pixel of claim 11, arranged to form an image sensor, which is backside illuminated so that said MIM capacitor and any metal routing layers do not block incident illumination and thus do not reduce optical fill factor.

13. The pixel of claim 1, wherein said capacitance C_int comprises a metal-oxide-metal (MOM) capacitor.

14. The pixel of claim 13, arranged to form an image sensor, which is backside illuminated so that said MOM capacitor and any metal routing layers do not block incident illumination and thus do not reduce optical fill factor.

15. The pixel of claim 3, further comprising:

a bias transistor that provides bias current to said source-follower transistor;

sampling capacitances and processing circuitry located on a different layer from said layer one;

said processing circuitry arranged to store at least said HG reset level, said HG signal level, and said LG signal level on said sampling capacitances as said levels become available on said output node; and

said processing circuitry further arranged to route the voltages stored on said sampling capacitances to at least one read node, buffer the voltage on said at least one read node, and multiplex it on at least one vertical bus line during pixel array readout, said pixel array readout occurring during said integration phase.

16. The pixel of claim 15, forming a pixel array consisting of rows and columns, wherein:

the process of storing each of said HG reset level, said HG signal level, and said LG signal level on said sampling capacitances occurs simultaneously for all pixels of said pixel array;

said pixel processing circuitry further comprises at least one read buffer and at least one row select switch controlled by a row select signal;

the input of said at least one read buffer is connected to said at least one read node;

the output of said at least one read buffer is coupled to said at least one vertical bus line through said row select switch;

the row select signal selects one row of said pixel array for a duration of one row time such that, for each pixel in the selected row, the buffered voltage on said at least one read node is multiplexed on said at least one vertical bus line; and

pixel rows are selected sequentially during said pixel array readout until all pixels of said pixel array are read out.

17. The pixel of claim 16, wherein said at least one read buffer is a source follower.

18. The pixel of claim 15, wherein said sampling capacitances are trench capacitors.

19. The pixel of claim 16, wherein one plate of said sampling capacitances is common and is connected to a third constant potential.

20. The pixel of claim 19, wherein said processing circuitry comprises switching elements coupled to said sampling capacitances, said switching elements actuated to store at least said HG reset level, said HG signal level, and said LG signal level, on said sampling capacitances.

21. The pixel of claim 20, wherein said switching elements are operated to read the voltages stored on said sampling capacitances on said at least one read node, said voltages read out within said row time.

22. The pixel of claim 15, further comprising at least one aggregation switch that connects said read nodes of neighboring pixels in the horizontal and/or vertical direction, said aggregation switches optionally remaining on during said pixel array readout to effect pixel aggregation.

23. The pixel of claim 15, wherein said pixel is a vertically integrated circuit structure, consisting of said layer one, further comprising a second layer on which said processing circuitry resides, and a third layer on which said sampling capacitances reside.

24. The pixel of claim 16, wherein:

said sampling capacitances comprise C_{s_hg} and C_{r_hg};

said sampling capacitances C_{s_hg} and C_{r_hg} are connected to a shared HG node;

said shared HG node is coupled to said output node through a HG sampling switch;

one of said sampling capacitances C_{s_hg} and C_{r_hg} is connected to a third constant potential and the other of said sampling capacitances C_{s_hg} and C_{r_hg} is connected to a HG CDS node;

said HG CDS node is coupled to a reference voltage through a HG clamp switch; and

said HG CDS node is coupled to said read node through a HG select switch.

25. The pixel of claim 24, wherein:

said HG sampling switch and said HG clamp switch are closed and said HG select switch and said row select switch are open while said HG reset level is available at said output node;

said HG sampling switch is closed and said HG clamp switch, said HG select switch, and said row select switch are open while said HG signal level is available at said output node, thereby causing the voltage at said HG CDS node to be proportional to the difference between said HG signal level and said HG reset level; and

said HG sampling switch and said HG clamp switch are open and said HG select switch and said row select switch are closed during said pixel array readout.

26. The pixel of claim 24, wherein:

said sampling capacitances further comprise C_{s_lg} and C_{r_lg};

said sampling capacitances C_{s_lg} and C_{r_lg} are connected to a shared LG node;

said shared LG node is coupled to said output node through a LG sampling switch;

one of said sampling capacitances C_{s_lg} and C_{r_lg} is connected to a fourth constant potential and the other of said sampling capacitances C_{s_lg} and C_{r_lg} is connected to a LG UDS node;

said LG UDS node is coupled to a reference voltage through a LG clamp switch; and

said LG UDS node is coupled to said read node through a LG select switch.

27. The pixel of claim 26, wherein:

said LG sampling switch and said LG clamp switch are closed and said LG select switch and said row select switch are open while said LG reset level is available at said output node;

said LG sampling switch is closed and said LG clamp switch, said LG select switch, and said row select switch are open while said LG signal level is available at said output node, thereby causing the voltage at said LG UDS node to be proportional to the difference between said LG signal level and said LG reset level; and

said LG sampling switch, said LG clamp switch, and said HG select switch are open and said LG select switch and said row select switch are closed during said pixel array readout.

28. The pixel of claim 24, wherein:

said sampling capacitances further comprise C_{s_lg};

said sampling capacitance C_{s_lg} is connected between a LG sampling node and a fourth constant potential;

said LG sampling node is coupled to said output node through a LG clamp switch;

said LG sampling node is coupled to said read node through a LG select switch;

said LG clamp switch is closed and said LG select switch and said row select switch are open while said LG signal level is available at said output node; and

said LG clamp switch and said HG select switch are open and said LG select switch and said row select switch are closed during pixel array readout.

29. The pixel of claim 1, further comprising circuitry which subtracts said HG reset level from said HG signal level to effect correlated double sampling (CDS).

30. The pixel of claim 29, wherein said circuitry resides in the pixel, in the column, or off-chip.

31. The pixel of claim 1, further comprising circuitry which subtracts said LG reset level from said LG signal level to effect correlated double sampling (CDS).

32. The pixel of claim 31, wherein said circuitry comprises full frame memory.

33. The pixel of claim 1, further comprising circuitry which subtracts said LG reset level from said LG signal level to effect uncorrelated double sampling (UDS), wherein, during each row readout, the LG reset level of the current frame is subtracted from the LG signal level of the previous frame.

34. The pixel of claim 33, wherein said circuitry resides in the pixel, in the column, or off-chip.