METHOD AND SYSTEM FOR CARRYING OUT TIMING RELATED TASKS

• US 20190327697A1
• Filed: 11/24/2017
• Published: 10/24/2019
• Est. Priority Date: 11/25/2016
• Status: Active Grant

• Current Assignee: Illinois Advanced Research Center At Singapore Limited, Singapore University Of Technology And Design
• Original Assignee: Singapore University Of Technology And Design
• Inventors: YAU, David K.Y., LI, Yang, TAN, Rui, VISWANATHAN, Sreejaya
• Granted Patent: US 10,841,885 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 29/18 Indicating phase sequence; Indicating synchronism
• CPC Class Codes: G06F 2218/16 by matching signal segments
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04J 3/0661 using timestamps
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04W 56/00 Synchronisation arrangements
• CPC Class Codes: H04W 56/001 Synchronization between nodes

Abstract

Embodiments of the present invention provide a method and system for timing related tasks in IoT systems, for example, in relation to synchronisation of clocks and timestamping. It is desirable that the method and system is able to withstand external tampering in a manner which does not jeopardise the accuracy and integrity of time related tasks in the IoT systems.

Claims

1. A system for determining a timestamp using powerline voltage fluctuations, the system including one or more electronic devices configured to:

determine, at a first node, a first voltage fluctuation sequence;

determine, at a second node, the second node being on a power grid of the first node, a second voltage fluctuation sequence; and

compare, data of the first and second voltage fluctuation sequences, to determine a clock offset between the first and second nodes,

wherein each fluctuation sequence is a timestamp.

2. The system of claim 1, wherein each node includes a sensor to determine voltage fluctuations from either the node or a source in close proximity to the node.

3. The system of either claim 1 or 2, wherein the second node includes a timing apparatus for timestamping the clock offset, the timing apparatus being either a global navigation satellite system (GNSS) receiver or an atomic clock.

4. The system of any of claims 1 to 3, wherein the clock offset is determined using the formula:

i*=argmin<sub>iϵ

[1,m−

n+1]</sub> dissimilarity(f,g[i;

i+n−

1])

5. The system of any of claims 1 to 4, wherein the second node further includes a voltage sensor for determining voltage fluctuations at a power outlet of the second node.

6. The system of any of claims 1 to 5, wherein data of the first and second voltage fluctuation sequences are processed to remove DC bias and high frequency spikes.

7. The system of any of claims 1 to 6, wherein the voltage fluctuations result from either ENF or EMR fluctuations.

8. A data processor implemented method for determining a timestamp using powerline voltage fluctuations, the method including:

determining, at a first node, a first voltage fluctuation sequence;

determining, at a second node, the second node being on a power grid of the first node, a second voltage fluctuation sequence; and

comparing, data of the first and second voltage fluctuation sequences, to determine a clock offset between the first and second nodes,

wherein each fluctuation sequence is a timestamp.

9. The method of claim 8, wherein each node includes a sensor to determine voltage fluctuations.

10. The method of either claim 8 or 9, wherein the second node includes a timing apparatus for timestamping the clock offset, the timing apparatus being either a global navigation satellite system (GNSS) receiver or an atomic clock.

11. The method of any of claims 8 to 10, wherein the clock offset is determined using the formula:

i*=argmin<sub>iϵ

[1,m−

n+1]</sub> dissimilarity(f,g[i;

i+n−

1])

12. The method of any of claims 8 to 11, wherein the second node further includes a voltage sensor for determining voltage fluctuations at a power outlet of the second node.

13. The method of any of claims 8 to 12, wherein the data of the first and second voltage fluctuation sequences is processed to remove DC bias and high frequency spikes.

14. The method of any of claims 8 to 13, wherein the voltage fluctuations result from either ENF or EMR fluctuations.

15. A non-transitory computer readable storage medium embodying thereon a program of computer readable instructions which, when executed by one or more processors of a first node in communication with at least one other processor of a second node, cause the first node to carry out a method for determining a timestamp using powerline voltage fluctuations, the method embodying the steps of:

receiving, at a first node, first data of a first voltage fluctuation sequence at a second node, the second node being on a power grid of the first node;

determining, at the first node, second data of a second voltage fluctuation sequence; and

comparing, the first and second data, to determine a clock offset between the first and second nodes,

wherein each fluctuation sequence is a timestamp.

16. A system for synchronising clocks, the system including one or more electronic devices that:

determine, at a first node, a first node marker and a first node clock value;

transmit, from the first node, a first data packet including the first node clock value and the first node marker;

determine, at a second node, a second node marker and a second node clock value;

receive, at the second node, the first data packet;

synchronise, at the second node, both the first node clock value and the second node clock value, and

determine, at the second node, an offset between the first node clock value and the second node clock value,

wherein the respective node markers are determined from minute fluctuations of a cycle length of an electric voltage signal at each respective node.

17. The system of claim 16, the system including one or more electronic devices that further transmit, from the second node, a second data packet including the offset.

18. The system of either claim 16 or 17, wherein each respective marker is a vector of successive AC cycle lengths of the electric voltage signal at each respective node.

19. The system of any of claims 16 to 18, the system including one or more electronic devices that further determine, at the second node, of a power grid phase of the first node, wherein determination of the power grid phase includes use of a decoding algorithm.

20. A data processor implemented method for synchronising clocks, the method comprising:

determining, at a first node, a first node marker and a first node clock value;

transmitting, from the first node, a first data packet including the first node clock value and the first node marker;

determining, at a second node, a second node marker and a second node clock value;

receiving, at the second node, the first data packet;

synchronising, at the second node, both the first node clock value and the second node clock value, and

determining, at the second node, an offset between the first node clock value and the second node clock value,

wherein the respective node markers are determined from minute fluctuations of a cycle length of an electric voltage signal at each respective node.

21. A non-transitory computer readable storage medium embodying thereon a program of computer readable instructions which, when executed by one or more processors coupled to a first node in communication with at least one other processor coupled to a second power node, cause the first node to carry out a method for synchronising clocks, the method embodying the steps of:

determining, at a first node, a first node marker and a first node clock value, the first node marker and the first node clock value being included in a first data packet;

receiving, from a second node, a second data packet including a second node clock value and a second node marker;

synchronising, at the first node, both the first node clock value and the second node clock value, and

determining, at the first node, an offset between the first node clock value and the second node clock value,

wherein the respective node markers are determined from minute fluctuations of a cycle length of an electric voltage signal at each respective node.

22. A system for determining a grid phase of a device, the system including one or more electronic devices that:

transmits, from the device, a pre-determined number of AC cycle lengths;

receives, at a centralised server, the pre-determined number of AC cycle lengths on all three grid phases;

defines, at the centralised server, a TiF length;

applies, at the centralised server, a sliding window to extract multiple TiF signatures from a trace of the device;

compares, at the centralised server, each TiF signature against a centralised server trace; and

identifies, at the centralised server, the grid phase of the device.

23. A data processor implemented method for determining a grid phase of a device, the method comprising:

transmitting, from the device, a pre-determined number of AC cycle lengths;

receiving, at a centralised server, the pre-determined number of AC cycle lengths on all three grid phases;

defining, at the centralised server, a TiF length;

applying, at the centralised server, a sliding window to extract multiple TiF signatures from a trace of the device;

comparing, at the centralised server, each TiF signature against a centralised server trace; and

identifying, at the centralised server, the grid phase of the device.