SYSTEM AND METHOD FOR MANUFACTURE OF CIRCUIT BOARDS

• US 20190327837A1
• Filed: 04/16/2019
• Published: 10/24/2019
• Est. Priority Date: 04/18/2018
• Status: Active Grant

• Current Assignee: University of Hawai'i
• Original Assignee: University of Hawai'i
• Inventors: Garmire, David, Zhou, Jie, Oyama, Tamra
• Granted Patent: US 10,750,618 B2
• Time in Patent Office: Days
• CPC Class Codes: B33Y 80/00 Products made by additive manufacturing
• CPC Class Codes: H05K 1/0284 Details of three-dimensional rigid printed circuit boards H05K1/119 takes precedence; shaping of the substrate H05K3/0014
• CPC Class Codes: H05K 1/09 Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H05K 2201/0129 Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
• CPC Class Codes: H05K 2203/0557 Non-printed masks
• CPC Class Codes: H05K 2203/1147 Sealing or impregnating, e.g. of pores
• CPC Class Codes: H05K 2203/128 Molten metals, e.g. casting thereof, or melting by heating and excluding molten solder spraying droplets of molten metal H05K2203/1344
• CPC Class Codes: H05K 2203/308 Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
• CPC Class Codes: H05K 3/0073 Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
• CPC Class Codes: H05K 3/101 by casting or moulding of conductive material
• CPC Class Codes: H05K 3/184 using masks
• CPC Class Codes: H05K 3/281 by means of a preformed insulating foil H05K3/284 takes precedence
• CPC Class Codes: H05K 3/381 by special treatment of the substrate
• CPC Class Codes: H05K 3/387 for electroless plating H05K3/4661 takes precedence

Abstract

Methods, systems, and apparatus for fabricating a circuit board. The method includes fabricating, using an additive manufacturing device, a trace layer, a sacrificial layer, a rail layer and a lid. The method includes placing the sacrificial layer on the trace layer such that the raised traces protrude through corresponding openings of the sacrificial layer. The method includes depositing a conductive material on top of the sacrificial layer and the plurality of traces. The method includes removing the sacrificial layer from the trace layer and placing the rail layer on the trace layer such that the raised traces align with the corresponding openings of the rail layer. The method includes connecting one or more electrical components and melting a sealing sheet on top of the rail layer and the electrical components to reinforce connections and to provide protection. The method includes placing the lid on top of the sealing sheet.

Claims

1. A method for fabricating a circuit board, the method comprising:

fabricating, using an additive manufacturing device, a trace layer, a sacrificial layer, and a rail layer, the trace layer having a plurality of raised traces, the sacrificial layer having a plurality of openings corresponding to the plurality of raised traces of the trace layer, and the rail layer having a plurality of openings corresponding to the plurality of raised traces of the trace layer and one or more recesses for receiving electrical components;

placing the sacrificial layer on top of the trace layer such that the plurality of raised traces of the trace layer align with the corresponding plurality of openings of the sacrificial layer and protrude through the corresponding plurality of openings of the sacrificial layer;

depositing a conductive material on top of the sacrificial layer and the plurality of traces of the trace layer;

removing the sacrificial layer from the trace layer;

placing the rail layer on top of the trace layer such that the plurality of raised traces of the trace layer align with the corresponding plurality of openings of the rail layer;

connecting one or more electrical components to be in electrical communication with the conductive material by placing the electrical components in the respective one or more recesses of the rail layer; and

melting a sealing sheet on top of the rail layer and the electrical components to reinforce connections between the electrical components and the conductive material and to provide elemental protection.

2. The method of claim 1, wherein the trace layer and the rail layer each have aligning header openings configured to receive a pin header, and

wherein the method further comprises connecting a plurality of pin headers to the conductive material covering the plurality of raised traces via the header openings.

3. The method of claim 2, wherein fabricating the trace layer includes fabricating one or more pin stoppers located proximal to respective header openings, the one or more pin stoppers configured to be covered by the conductive material and maintain connection with the respective pin header when a force is exerted against the pin header causing the pin header to move within the header opening.

4. The method of claim 1, further comprising:

fabricating, using an additive manufacturing device, a lid; and

placing the lid on top of the sealing sheet while the sealing sheet is warm, the lid configured to reinforce connections between the electrical components and the conductive material and to provide elemental protection.

5. The method of claim 1, wherein the additive manufacturing device is a 3D printer.

6. The method of claim 1, wherein the additive manufacturing device uses a non-toxic material to fabricate the trace layer, the sacrificial layer, and the rail layer.

7. The method of claim 1, further comprising removing the conductive material from the sacrificial layer, and melting the sacrificial layer to reuse a material the sacrificial layer is made of.

8. The method of claim 1, further comprising melting a second sealing sheet below the trace layer to provide further elemental protection.

9. A method for fabricating a multilayer circuit board, the method comprising:

fabricating, using an additive manufacturing device, a first trace layer, a second trace layer, a sacrificial layer, and a rail layer, the first trace layer having a plurality of vias, the second trace layer having a plurality of raised traces and a plurality of openings corresponding to the plurality of vias, the sacrificial layer having a plurality of openings corresponding to the plurality of raised traces of the second trace layer, and the rail layer having a plurality of openings corresponding to the plurality of raised traces of the second trace layer and one or more recesses for receiving electrical components;

depositing a conductive material onto at least a portion of the first trace layer, including the plurality of vias;

placing the sacrificial layer on top of the second trace layer such that the plurality of raised traces of the second trace layer align with the corresponding plurality of openings of the sacrificial layer and protrude through the corresponding plurality of openings of the sacrificial layer;

depositing the conductive material onto the sacrificial layer and the plurality of traces of the second trace layer;

removing the sacrificial layer from the second trace layer;

placing the second trace layer on top of the first trace layer such that the plurality of vias of the first trace layer align with and protrude from the corresponding plurality of openings of the second trace layer;

placing the rail layer on top of the second trace layer such that the plurality of raised traces of the second trace layer align with the corresponding plurality of openings of the rail layer;

connecting one or more electrical components to be in electrical communication with the conductive material by placing the electrical components in the respective one or more recesses of the rail layer; and

melting a sealing sheet on top of the rail layer and the electrical components to reinforce connections between the electrical components and the conductive material and to provide elemental protection.

10. The method of claim 9, wherein the first trace layer and the rail layer each have aligning header openings configured to receive a pin header, and

wherein the method further comprises inserting a plurality of pin headers to respective header openings to connect the pin headers to the conductive material covering the plurality of raised traces and the plurality of vias.

11. The method of claim 9, wherein the second trace layer is placed on top of the first trace layer prior to placing the sacrificial layer on top of the second trace layer and depositing the conductive material onto the sacrificial layer and the plurality of traces of the second trace layer.

12. The method of claim 9, wherein the second trace layer is placed on top of the first trace layer after the sacrificial layer is placed on top of the second trace layer and the conductive material is deposited onto the sacrificial layer and the plurality of traces of the second trace layer.

13. The method of claim 9, further comprising:

fabricating, using an additive manufacturing device, a lid; and

placing the lid on top of the sealing sheet while the sealing sheet is warm, the lid configured to reinforce connections between the electrical components and the conductive material and to provide elemental protection.

14. The method of claim 9, wherein the additive manufacturing device is a 3D printer.

15. The method of claim 9, wherein the additive manufacturing device uses a non-toxic material to fabricate the trace layer, the sacrificial layer, and the rail layer.

16. The method of claim 9, further comprising removing the conductive material from the sacrificial layer, and melting the sacrificial layer to reuse a material the sacrificial layer is made of.

17. The method of claim 9, further comprising melting a second sealing sheet below the trace layer to provide further elemental protection.

18. A method for fabricating a circuit board, the method comprising:

fabricating, using an additive manufacturing device, a trace layer, a gap layer onto the trace layer, and a sacrificial layer onto the gap layer, the gap layer being printed above the trace layer and not directly onto the trace layer such that extruded filament from the additive manufacturing device cools before touching the trace layer and creating a non-permanent bond to the trace layer;

fabricating, using the additive manufacturing device, a rail layer;

depositing a conductive material on top of the sacrificial layer and a plurality of traces of the trace layer;

breaking the non-permanent bond established by the gap layer to remove the sacrificial layer from the trace layer; and

placing the rail layer on top of the trace layer such that the plurality of raised traces of the trace layer align with a corresponding plurality of openings of the rail layer.

19. The method of claim 18, further comprising:

connecting one or more electrical components to be in electrical communication with the conductive material by placing the electrical components in respective one or more recesses of the rail layer;

melting a sealing sheet on top of the rail layer and the electrical components to reinforce connections between the electrical components and the conductive material and to provide elemental protection.

20. The method of claim 19, wherein the trace layer and the rail layer each have aligning header openings configured to receive a pin header, and wherein the method further comprises:

connecting a plurality of pin headers to the conductive material covering the plurality of raised traces via the header openings;

fabricating, using an additive manufacturing device, a lid; and

placing the lid on top of the sealing sheet while the sealing sheet is warm, the lid configured to reinforce connections between the electrical components and the conductive material and to provide elemental protection.