Radar Hardware Accelerator

• US 20190331765A1
• Filed: 06/14/2019
• Published: 10/31/2019
• Est. Priority Date: 06/16/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Rao, Sandeep, Ramasubramanian, Karthik, Prathapan, Indu, Ganesan, Raghu, Gupta, Pankaj
• Granted Patent: US 11,579,242 B2
• Time in Patent Office: Days
• CPC Class Codes: G01S 13/34 using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
• CPC Class Codes: G01S 13/42 Simultaneous measurement of distance and other co-ordinates indirect measurement G01S13/46
• CPC Class Codes: G01S 13/584 adapted for simultaneous range and velocity measurements
• CPC Class Codes: G01S 13/931 of land vehicles
• CPC Class Codes: G01S 7/003 Transmission of data between radar, sonar or lidar systems and remote stations
• CPC Class Codes: G01S 7/023 Interference mitigation, e.g. reducing or avoiding non-intentional interference with other HF-transmitters, base station transmitters for mobile communication or other radar systems, e.g. using electro-magnetic interference [EMI] reduction techniques auxiliary means for detecting or identifying radar signals or the like G01S7/021; means for anti-jamming G01S7/36
• CPC Class Codes: G01S 7/354 Extracting wanted echo-signals Doppler systems G01S13/50
• CPC Class Codes: G01S 7/356 involving particularities of FFT processing
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04L 27/103 Chirp modulation for spread spectrum techniques H04B1/69

Abstract

A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

Claims

1-20. -20. (canceled)

21. A radar hardware accelerator (HWA), comprising:

a fast Fourier transform (FFT) engine including;

a preprocessing block for generating preprocessed samples;

a windowing plus FFT block (windowed FFT block) for multiplying the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples;

a post-processing block for computing a magnitude of the Fourier transformed samples; and

wherein the preprocessing block, the windowed FFT block, and the post-processing block are connected in one streaming series data path.

22. The HWA of claim 21, further comprising a constant false alarm rate (CFAR) engine in a CFAR detection path parallel to the streaming series data path including a log-magnitude pre-processing block and a CFAR detector for detecting radar target returns against a background.

23. The HWA of claim 21, wherein the pre-processing block, the windowed FFT block and the post-processing block include independent enable (EN) circuits to provide independent muxing controls that enable/bypass for any combination of the pre-processing block, the windowed FFT block and the post-processing block.

24. The HWA of claim 21, further comprising a substrate that provides at least a semiconductor surface, wherein the HWA is formed in the semiconductor surface.

25. The HWA of claim 21, wherein the ADC buffers and the output buffers are both split memories.

26. The HWA of claim 21, wherein the CFAR detection path shares at least one of a shared memory and logic with the FFT engine.

27. The HWA of claim 21, wherein the preprocessing block provides interference mitigation.

28. The HWA of claim 21, wherein the preprocessing block provides finite pulse response (FIR) filtering.

29. The HWA of claim 21, wherein the preprocessing block multiplies a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buggers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT).

30. A radar sub-system, comprising:

a split accelerator local memory including ADC input buffers (ADC buffers) for storing radar data sample streams, and output buffers;

a radar hardware accelerator (HWA) coupled to the ADC buffers for receiving the radar data sample streams and for processing the radar data sample streams, the HWA including;

a fast Fourier transform (FFT) engine including;

a pre-processing block for generating pre-processed samples;

a windowing plus FFT block (windowed FFT block) for multiplying the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples;

a post-processing block for computing a magnitude of the Fourier transformed samples for generating post-processed radar data, wherein the pre-processing block, the windowed FFT block, and the post-processing block are connected in one streaming series data path, and wherein an output of the post-processing block is coupled to an input of the output buffers for transferring the post-processed radar data to the output buffers, and

a parameter-set configuration memory coupled to a state machine both coupled by a bus to the FFT engine for sequencing parameters sets for execution of a chained sequence of operations and data transfers between the accelerator local memory and an external memory for controlling the pre-processing block, the windowed FFT block and the post-processing block.

31. The radar sub-system of claim 30, wherein the state machine is a parameter-set based state machine wherein the parameter-sets are programmable, the parameter-sets for configuring the HWA to perform a certain set of the operations, and wherein a sequence of executing the parameter-sets is defined.

32. The radar sub-system of claim 31, wherein the radar sub-system is configured to utilize 2D memory indexing, wherein each of the parameter-sets performs a specific one of the operations on multiple ones of the radar data sample streams including a first radar data sample stream and a subsequent second radar data sample stream, and wherein a separation between subsequent samples of each of the radar data sample streams, a separation between an initial sample of the first radar data sample stream and an initial sample of the second radar data sample stream, and a number of the radar data sample streams for each of the operations is configurable via the parameter-sets.

33. The radar sub-system of claim 30, further comprising a constant false alarm rate (CFAR) engine in a CFAR detection path parallel to the streaming series data path including a log-magnitude pre-processing block and CFAR detector for detecting radar target returns against a background.

34. The radar sub-system of claim 30, wherein the ADC buffers and the output buffers are both split memories.

35. The radar sub-system of claim 30, further comprising a substrate that provides at least a semiconductor surface, wherein the HWA is formed in the semiconductor surface.

36. The radar sub-system of claim 30, wherein the pre-processing block, the windowed FFT block and the post-processing block include independent enable (EN) circuits to provide independent muxing controls that enable/bypass for any combination of the pre-processing block, the windowed FFT block and the post-processing block.

37. The radar sub-system of claim 30, wherein the preprocessing block provides interference mitigation.

38. The radar sub-system of claim 30, wherein the preprocessing block provides finite pulse response (FIR) filtering.

39. The radar sub-system of claim 30, wherein the preprocessing block multiplies a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buggers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT).

40. A method of (FMCW) radar signal processing using a radar hardware accelerator (HWA), comprising:

streaming post-processed radar data to output buffers;

transferring range fast Fourier transform (FFT) data from the output buffers to an external memory via direct memory accesses (DMA), the DMA being triggered automatically by the HWA;

repeating the streaming and the transferring for radar data sample streams received by multiple antennas and across multiple chirps;

wherein further processing is performed on the range FFT data originating from the multiple antennas and across the multiple chirps, comprising;

transferring from the external memory in blocks to the output buffers, each the block including data for a first range gate and at least a second range gate;

performing multiple doppler FFT'"'"'s using the HWA corresponding to the first range gate, wherein the doppler FFTs are computed for each of the multiple antennas in the first range gate;

performing an absolute value operation on result of the doppler FFT'"'"'s for each of the multiple antennas corresponding to the first range gate, and summing results of the the absolute value operation across the multiple antennas, and

repeating the further processing on subsequent data blocks from the data blocks corresponding to at least the second range gate.

41. The method of claim 40, wherein the transferring the range FFT data is performed in a transpose fashion.

42. The method of claim 40, further comprising detecting radar target returns against a background using a constant false alarm rate (CFAR) engine in a CFAR detection path parallel to a streaming series data path including a log-magnitude pre-processing block and a CFAR detector.

43. The method of claim 40, further comprising indexed memory addressing for data transfers to and from the HWA.

44. The method of claim 40, wherein the FFT engine comprises:

a preprocessing block for generating pre-processed samples;

a windowing plus FFT block (windowed FFT block) for multiplying the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples, and

a post-processing block for computing a magnitude of the Fourier transformed samples for generating the post-processed radar data;

wherein the pre-processing block, the windowed FFT block, and the post-processing block are connected in one streaming series data path.

45. The method of claim 44, wherein the pre-processing block, the windowed FFT block and the post-processing block include independent enable (EN) circuits to provide independent muxing controls that enable/bypass for any combination of the pre-processing block, the windowed FFT block and the post-processing block.

46. The method of claim 40, further comprising 2D memory indexing, wherein each of multiple parameter-sets performs a specific operation on multiple ones of the radar data sample streams including a first radar data sample stream and a subsequent second radar data sample stream, and wherein a separation between subsequent samples of each of the radar data sample streams, a separation between an initial sample of the first radar data sample stream and an initial sample of the second radar data sample stream, and a number of the radar data sample streams for each of the operations is configurable via the parameter-sets.