Clocking Synchronization Method and Apparatus

• US 20190332139A1
• Filed: 06/03/2019
• Published: 10/31/2019
• Est. Priority Date: 06/03/2019
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rapeta, Jagannadha Rao V. V. V., Hunsaker, Mikal, Swartz, Ronald, Fulton, Robert, Elzinga, L. Mark, Park, Young Min, Mulvihill, David R.
• Granted Patent: US 11,144,088 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.

Claims

1. A communication node, comprising:

a phase lock loop (PLL) arranged to generate a clock;

a phase frequency detector (PFD) coupled to the PLL to determine parts-per-million (PPM) differences between the PLL and a recovered clock, during a start static phase measurement (SSPM) sequence of a clock training period; and

a static phase measurement (SPM) controller coupled to the PLL and the auxiliary loop PFD, and arranged to measure static phase of the recovered clock, receive the PPM differences determined, and provide PPM correction to the PLL to compensate for the PPM differences determined during subsequent clocking synchronization.

2. The communication node of claim 1, wherein the clocking synchronization comprises spread spectrum clocking (SSC) synchronization;

the PLL includes a SSC modulator; and

the SPM controller is further arranged to detect a 0 PPM or slope change event in the recovered clock, and in response to a detection of the 0 PPM event, provide a SSC enable signal to the SSC modulator.

3. The communication node of claim 2, wherein the SPM controller is further arranged to provide SSC pattern data to the SSC modulator;

and wherein the SSC modulator generates SSC adjustments, based at least in part on the SSC pattern data.

4. The communication node of claim 2, wherein the PLL further comprises a digitally controlled oscillator (DCO), and wherein to determine the PPM differences between the recovered clock and the PLL, the auxiliary loop PFD determines the PPM differences between the DCO and the recovered clock.

5. The communication node of claim 4, wherein the PLL generates the SSC via control of the DCO by the SSC modulator.

6. The communication node of claim 4, wherein the PLL includes a feedback divider coupled to the DCO;

and the PLL generates the SSC using the feedback divider.

7. The communication node of claim 2 further comprising a local controller to receive 0 PPM event messages from another communication node, and in response to the receipt, generates a SSC sync signal for the SPM controller;

wherein the other communication node is a host, and the communication node is an endpoint.

8. The communication node of claim 2, wherein the SPM controller is further arranged to receive a SSC sync signal from another communication node;

wherein the other communication node is a host, and the communication node is an endpoint.

9. The communication node of claim 1, wherein the PLL is initially closed with a local reference clock (Refclk), and the PLL further comprises a feed forward correction block to receive and apply the PPM correction to compensate for the PPM differences determined.

10. The communication node of claim 1, wherein the PLL further comprises a fractional modulator;

wherein the SPM controller is further arranged to provide factional modulation pattern data to the fractional modulator; and

wherein the fractional modulator is arranged to generate fractional correction, based at least in part on factional modulation pattern data.

11. The communication node of claim 1, wherein the communication node is a peripheral component interconnect express (PCIe) communication node.

12. A method for communication, comprising:

performing, by an endpoint communication node, clock training handshake with a host communication node;

entering, by the endpoint communication node, a clock training period, on successful performance of the clock training handshake;

entering, by the endpoint communication node, a start static phase measurement (SSPM) sequence of clock training period, and receiving clocking pattern from the host communication node; and

processing, by the endpoint communication node, the clocking pattern to determine aprts-per-million (PPM) differences with the host communication node, to be applied to compensate for the PPM differences determined during subsequent clocking synchronization.

13. The method of claim 12, wherein clocking synchronization comprises spread spectrum clocking (SSC) synchronization, and the clocking pattern comprises SSC pattern;

wherein the method further comprises;

locking, by the endpoint communication node, onto the SSC pattern;

enabling, by the endpoint communication node, local SSC modulation when static phase offset or slope change matches; and

monitoring, by the endpoint communication node, continuously the SSC pattern, and adjusting its SSC pattern to match the monitored SSC pattern for subsequent generation of SSC signals.

14. The method of claim 12, wherein clocking synchronization comprises spread spectrum clocking (SSC) synchronization, and the clocking pattern comprises SSC pattern;

wherein the method further comprises;

enabling, by the endpoint communication node, local SSC modulation when a SSC sync signal arrives; and

monitoring, by the endpoint communication node, continuously the SSC pattern, and adjusting its SSC pattern to match the monitored SSC pattern for subsequent generation of SSC signals.

15. The method of claim 12, wherein clocking synchronization comprises spread spectrum clocking (SSC) synchronization, and the clocking pattern comprises SSC pattern;

wherein the method further comprises;

enabling, by the endpoint communication node, local SSC modulation after compensating for SSC enable detection;

enabling, by the endpoint communication node, local SSC modulation when static phase offset matches; and

monitoring, by the endpoint communication node, continuously the SSC pattern, and adjusting its SSC pattern to match the monitored SSC pattern for subsequent generation of SSC signals.

16. The method of claim 12, wherein the endpoint communication node is a peripheral component interconnect express (PCIe) endpoint communication node.

17. A communication node, comprising:

a physical layer having a logical sub-block, and an electrical sub-block;

wherein the logical sub-block includes clock and link training and management logic arranged to;

perform clock training handshake with an endpoint communication node;

instruct the endpoint communication node to start static phase measurement as part of the clock training, on successful completion of the clock training handshake;

provide clock pattern to the endpoint communication node until receipt of an acknowledgement from the endpoint communication node; and

instruct the endpoint communication node to start clocking synchronization, on receipt of the acknowledgment.

18. The communication node of claim 17, wherein clocking synchronization comprises spread spectrum clocking (SSC) synchronization;

the clock and link training and management logic is further arranged to provide the endpoint communication node with SSC pattern, on instructing endpoint communication node to start SSC synchronization;

wherein the acknowledgement is a first acknowledgment,; and

wherein the clock and link training and management logic is arranged to provide the endpoint communication node with the SSC pattern, until receipt of a second acknowledgment.

19. The communication node of claim 18, wherein clock and link training and management logic is further arranged to proceed to cooperate with the endpoint communication node to perform link training on receipt of the second acknowledgment.

20. The communication node of claim 17, wherein the communication node is a peripheral component interconnect express (PCIe) host communication node.

21. A communication node, comprising:

a physical layer having a logical sub-block, and an electrical sub-block;

wherein the logical sub-block includes clock and link training and management logic arranged to;

perform clock training handshake with a host communication node;

receive instruction from the host communication node to start static phase measurement as part of the clock training, on successful completion of the clock training handshake;

receive clock pattern from the host communication node;

provide an acknowledgement to the host communication node on successful completion of the static phase measurement;

receive instruction from the host communication node to start clocking synchronization; and

start clocking synchronization to the host communication node.

22. The communication node of claim 21, wherein clocking synchronization comprises spread spectrum clocking (SSC) synchronization;

the clock and link training and management logic is further arranged to receive from the endpoint communication node with SSC pattern;

wherein the acknowledgement is a first acknowledgment,; and

wherein the clock and link training and management logic is arranged to provide to the host communication node a second acknowledgment, on completion of SSC synchronization.

23. The communication node of claim 22, wherein clock and link training and management logic is further arranged to proceed to cooperate with the host communication node to perform link training on provision of the second acknowledgment.

24. The communication node of claim 21, wherein the communication node is a peripheral component interconnect express (PCIe) endpoint communication node.