APPARATUSES AND METHODS TO CONTROL MEMORY OPERATIONS ON BUFFERS

• US 20190332284A1
• Filed: 07/09/2019
• Published: 10/31/2019
• Est. Priority Date: 05/31/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mohammadzadeh, Ali, Hoei, Jung Sheng, Srinivasan, Dheeraj, Grunzke, Terry M.
• Granted Patent: US 10,936,210 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

Claims

1. An apparatus, comprising:

a host configured to control performance of a memory operation on data in a buffer, the host comprising a processor, a system controller, a memory and bus controller, a peripheral and bus controller, and a host memory;

a memory device including a buffer; and

a set feature interface internal to the host and associated with the system controller, wherein the set feature interface includes a plurality of features and a plurality of options, the plurality of features and the plurality of options are selectively enabled via input commands, and wherein the input commands are issued to the set features interface via the host, the processor, the system controller, the memory and bus controller, and the peripheral and bus controller.

2. The apparatus of claim 1, wherein one of the plurality of features is a direction to a selection of page buffer operation, a plane selection, a buffer selection of a single cache, and a buffer selection of a multiple cache.

3. The apparatus of claim 2 wherein the feature is to direct a selection of a page buffer operation, the page buffer operation is performed on the buffer.

4. The apparatus of claim 3, wherein the selection of a page buffer operation includes a copy operation, a reset operation and a swap operation.

5. The apparatus of claim 2, wherein the feature is to direct a plane selection, wherein a particular plane is selectively enabled.

6. The apparatus of claim 5, wherein plane selection can select a single plane, a plurality of planes, and all planes.

7. The apparatus of claim 2, wherein the feature is to selectively enable a buffer selection of a particular single cache, wherein the option to select the particular single cache, the particular cache can be a secondary data cache or a primary data cache via the entry of one data value in a cache.

8. The apparatus of claim 2, wherein the feature is to direct a buffer selection to multiple cache simultaneously, wherein the option to select the multiple cache, the selected cache can be a secondary data cache and multiple primary data caches via entry of one data value in a cache.

9. The apparatus of claim 1, wherein a plurality of set features interfaces are maintained when the memory device includes a plurality of memory devices.

10. An apparatus comprising:

a memory device comprising a buffer and an array of memory cells, wherein the buffer comprises a number of first data caches and a number of second data cache;

a system controller configured to, in association with programming data from the buffer to the array of memory cells in a multiple phase programming process, control data movement among the number of first and second data caches; and

wherein the system controller is further configured to;

while data is being programmed from the buffer to the array of memory cells, receive a request to issue a program suspend command;

responsive to receiving the request to issue the program suspend command;

issue a first command to the memory device, wherein execution of the first command by the memory device includes moving a first portion of the data being programmed to the array from a secondary data cache to a primary data cache to prevent the first portion of the data from being programmed to the array;

subsequently to moving the first portion of the data from the secondary data cache to the primary data cache, issue a second command to the memory device to initiate a program suspend state and to perform an operation using the secondary data cache in which the first portion of data resided prior to being moved to the primary data cache; and

issue a third command following completion of the operation using the secondary data cache, wherein execution of the third command by the memory device includes moving the first portion of the data back to the primary data cache.

11. The apparatus of claim 10, wherein the system controller is further configured to issue a fourth command to the memory device;

wherein execution of the fourth command by the memory device includes termination of the program suspend state.

12. The apparatus of claim 11, wherein the fourth command is issued subsequently to execution by the memory device of the third command.

13. The apparatus of claim 12, wherein the fourth command is a program resume command.

14. The apparatus of claim 12, wherein the system controller is further configured to issue a fifth command is issued to program the first portion of data from the buffer to the array of memory cells.

15. The apparatus of claim 14, wherein the memory device is configured to prevent reprogramming to the array of a second portion of the data previously being programmed to the array prior to execution of the first command.

16. The apparatus of claim 10, wherein the apparatus comprises a host configured to provide the request to the system controller.

17. The apparatus of claim 16, wherein the memory device comprises a device controller configured to execute commands received by the memory device from the system controller.

18. An apparatus comprising:

a memory device comprising a buffer and an array of memory cells, wherein the buffer comprises a first data cache and a second data cache;

a host coupled to the memory device and configured to;

initiate a program suspend state by issuing a first command to the memory device to suspend execution by the memory device of a multiple phase programming operation that involves programming of data stored in the buffer to the array;

issue a second command during the program suspend state to move the data stored in the buffer to the host;

during the program suspend state, perform a memory operation using at least one of the first or second data cache of the buffer;

upon completion of the memory operation, execute a third command to move the data from the host back to the buffer; and

issue a fourth command to terminate the program suspend state such that the memory device resumes execution of the multiple phase programming operation.

19. The apparatus of claim 18, wherein the second command is a set feature command.

20. The apparatus of claim 18, wherein the at least one of the first or second data cache serve as an available memory resource to the host while the memory device is in the program suspend state.