DYNAMIC PROCESSOR CACHE TO AVOID SPECULATIVE VULNERABILITY
First Claim
1. A processor, comprising:
- a logic unit configured to execute multiple instructions, each of the multiple instructions being one of a speculative instruction or an architectural instruction;
a split cache comprising multiple lines, each line including a data accessed by an instruction and copied into the split cache from a memory address, wherein a line is identified as a speculative line for the speculative instruction, and as an architectural line for the architectural instruction; and
a cache manager configured to;
select a number of speculative lines to be allocated in the split cache, based on a current state of the processor,prevent an architectural line from being replaced by a speculative line based on a number of speculative lines allotted in the split cache, andmanage the number of speculative lines to be allocated in the split cache when the speculative instruction requests a data access based on the number of speculative lines relative to a number of architectural lines.
1 Assignment
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Accused Products
Abstract
A processor including a logic unit configured to execute multiple instructions being one of a speculative instruction or an architectural instruction is provided. The processor also includes a split cache comprising multiple lines, each line including a data accessed by an instruction and copied into the split cache from a memory address, wherein a line is identified as a speculative line for the speculative instruction, and as an architectural line for the architectural instruction. The processor includes a cache manager configured to select a number of speculative lines allocated in the split cache. The cache manager prevents an architectural line from being replaced by a speculative line based on a number of speculative lines allotted in the split cache, and manages the number of speculative lines to be allocated in the split cache based on the number of speculative lines relative to a number of architectural lines.
18 Citations
20 Claims
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1. A processor, comprising:
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a logic unit configured to execute multiple instructions, each of the multiple instructions being one of a speculative instruction or an architectural instruction; a split cache comprising multiple lines, each line including a data accessed by an instruction and copied into the split cache from a memory address, wherein a line is identified as a speculative line for the speculative instruction, and as an architectural line for the architectural instruction; and a cache manager configured to; select a number of speculative lines to be allocated in the split cache, based on a current state of the processor, prevent an architectural line from being replaced by a speculative line based on a number of speculative lines allotted in the split cache, and manage the number of speculative lines to be allocated in the split cache when the speculative instruction requests a data access based on the number of speculative lines relative to a number of architectural lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A cache, comprising:
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a management unit; a first plurality of architectural lines storing data fetched by an architectural instruction to be executed by a processor coupled with the cache, the architectural instruction, when executed, configured to modify an architecture of the cache; and a second plurality of speculative lines storing data fetched by a speculative instruction, wherein the speculative instruction is invalidated by the management unit, wherein a number of the first plurality of architectural lines and the second plurality of speculative lines is dynamically determined based on a state of the processor. - View Dependent Claims (16)
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17. A method, comprising:
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retrieving, with a fetch engine, a data associated with an instruction to be executed by a logic unit of a processor, from an external memory, wherein the instruction is one of a speculative instruction or an architectural instruction; copying the data from a memory address to a data in a speculative line in a split cache, when the data is fetched by a speculative instruction, and to an architectural line in the split cache when the data is fetched by an architectural instruction; selecting a number of speculative lines to be allocated in the split cache based on a current state of the processor; preventing an architectural line in the split cache from being replaced by a speculative line; and managing the number of speculative lines to be allocated in the split cache when a speculative instruction requests a data access based on the number of speculative lines relative to a number of architectural lines in the split cache. - View Dependent Claims (18, 19, 20)
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Specification