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SIDE CACHE

  • US 20190332382A1
  • Filed: 04/30/2018
  • Published: 10/31/2019
  • Est. Priority Date: 04/30/2018
  • Status: Active Grant
First Claim
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1. A device, comprising:

  • a processor configured to access data to execute multiple instructions;

    a first cache coupled to the processor, the first cache configured to hold a first data fetched from a memory by a first instruction that has been retired;

    a side cache coupled to the first cache and to the processor, the side cache configured to hold a second data fetched from the memory by a second instruction, wherein the second instruction has not been retired from the processor; and

    a cache management unit configured to move the second data from the side cache to the first cache when the second instruction is retired, the cache management unit further configured to discard the second data when it is determined that the second instruction is abandoned.

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