SIDE CACHE

• US 20190332382A1
• Filed: 04/30/2018
• Published: 10/31/2019
• Est. Priority Date: 04/30/2018
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Lesartre, Gregg B.
• Granted Patent: US 11,119,780 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification

Abstract

A device including a processor configured to access data to execute multiple instructions and a first cache coupled to the processor, are provided. The first cache is configured to hold a first data fetched from a memory by a first instruction that has been retired. The device also includes a side cache coupled to the first cache and to the processor, the side cache configured to hold a second data fetched from the memory by a second instruction, wherein the second instruction has not been retired from the processor. And the device includes a cache management unit configured to move the second data from the side cache to the first cache when the second instruction is retired, the cache management unit further configured to discard the second data when it is determined that the second instruction is abandoned.

Claims

1. A device, comprising:

a processor configured to access data to execute multiple instructions;

a first cache coupled to the processor, the first cache configured to hold a first data fetched from a memory by a first instruction that has been retired;

a side cache coupled to the first cache and to the processor, the side cache configured to hold a second data fetched from the memory by a second instruction, wherein the second instruction has not been retired from the processor; and

a cache management unit configured to move the second data from the side cache to the first cache when the second instruction is retired, the cache management unit further configured to discard the second data when it is determined that the second instruction is abandoned.

2. The device of claim 1, further comprising an instruction fetch unit configured to provide the first instruction and the second instruction to the processor, the instruction fetch unit further configured to associate a first tag to the first instruction and a second tag to the second instruction, wherein the first tag is lower than the second tag.

3. The device of claim 1, wherein the first instruction and the second instruction comprise a memory access instruction that reads a data portion from, or writes the data portion to a memory coupled to the processor, and wherein the data portion comprises the first data and the second data.

4. The device of claim 1, wherein the first data or the second data may be accessed by a third instruction executed by the processor.

5. The device of claim 1, wherein the cache management unit is configured to identify an access miss to the first data by a third instruction, and to provide the second data to the processor in response to an execution of the third instruction when the cache management unit identifies an access hit on the second data.

6. The device of claim 1, wherein the cache management unit is configured to evict a line in the first cache when the second instruction is retired.

7. The device of claim 1, wherein the cache management unit is configured to invalidate an entry in the side cache that is associated with an instruction that was fetched prior to a retiring instruction.

8. The device of claim 1, wherein the cache management unit is configured to add a timestamp to the second data when the second data is entered in the side cache, and to provide the second data to a requesting third instruction after a period of time, based on the timestamp.

9. The device of claim 1, wherein the processor comprises multiple processors sharing the first cache and the side cache, and wherein the first instruction comprises a first tag for a first processor that executes the first instruction, and the second instruction comprises a second tag for a second processor that executes the second instruction.

10. The device of claim 1, wherein an entry for the second data in the side cache is configured to hold a tag for each of multiple instructions that have accessed the second data before the second data is retired or is transferred to the first cache.

11. The device of claim 1, wherein the side cache further comprises a link list structure to hold a tag for an instruction that accesses the second data before the second data is retired or is transferred to the first cache.

12. The device of claim 1, wherein the cache management unit is configured to determine a tag of a speculative instruction that may be retired, the tag being indicative that a previous instruction with a lower tag is invalid.

13. A system, comprising:

a memory configured to store data; and

a central processing unit coupled to the memory, the central processing unit comprising;

a processor configured to access data to execute multiple memory access instructions;

a first cache coupled to the processor, the first cache configured to hold a first data copied into the first cache from the memory by a first memory access instruction that has been retired;

a side cache coupled to the first cache and to the processor, the side cache configured to hold a second data copied into the side cache from the memory by a second memory access instruction, wherein the second memory access instruction has not been retired from the processor; and

a cache management unit configured to move the second data from the side cache to the first cache when the second memory access instruction is retired, the cache management unit further configured to discard the second data when it is determined that the second memory access instruction is abandoned.

14. The system of claim 13, wherein the central processing unit further comprises an instruction fetch unit configured to provide the first memory access instruction and the second memory access instruction to the processor, the instruction fetch unit further configured to associate a first tag to the first memory access instruction and a second tag to the second memory access instruction, wherein the first tag is lower than the second tag.

15. The system of claim 13, wherein the cache management unit is configured to identify an access miss to the first data by a third memory access instruction, and to provide the second data to the processor in response to an execution of the third memory access instruction when the cache management unit identifies an access hit on the second data.

16. The system of claim 13, wherein the cache management unit is configured to add a timestamp to the second data when the second data is entered in the side cache, and to provide the second data to a third memory access instruction after a period of time, based on the timestamp.

17. A method, comprising:

fetching, by a processor, a first data from a memory for a first instruction to be executed by the processor;

retiring the first instruction from a processing schedule;

copying the first data in a first cache of the processor;

fetching a second data from the memory for a second instruction to be executed by the processor;

copying the first data to a side cache of the processor before the second instruction is retired from the processing schedule;

transferring, with a cache management unit in the processor, the second data from the side cache to the first cache when the second instruction is retired; and

discarding the second data when it is determined that the second instruction is abandoned before an execution by the processor.

18. The method of claim 17, further comprising identifying, with the cache management unit, an access miss to the first data by a third instruction, and to provide the second data to the processor in response to the execution of the third instruction when the cache management unit identifies an access hit on the second data.

19. The method of claim 17, further comprising evicting, with the cache management unit, a line in the first cache when the second instruction is retired.

20. The method of claim 17, further comprising invalidating, with the cache management unit, an entry in the side cache that is associated with an instruction that was fetched prior to a retiring instruction.