MEMORY CONTROLLER AND OPERATING METHOD THEREOF

• US 20190332436A1
• Filed: 12/03/2018
• Published: 10/31/2019
• Est. Priority Date: 04/26/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Joo Young
• Granted Patent: US 10,754,692 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

There are provided a memory controller and an operating method thereof. The memory controller includes a host interface layer for receiving a host program request and a host read request, a flash translation layer for generating and outputting a program command and a plurality of program addresses in response to the host program request, checking a program progress state for a program address corresponding to a target read address when the target read address corresponding to the host read request is included in the program addresses, and controlling a read operation on the target read address according to whether a program operation on the program address corresponding to the target read address has been completed, and a flash interface layer for transmitting a command and addresses, which are output from the flash translation layer, to a memory device.

Claims

1. An operating method of a memory controller, the method comprising:

transmitting a program command and a plurality of program addresses to a memory device in response to a host program request;

checking, when a target read address corresponding to a host read request is included in the program addresses, a program progress state for a program address corresponding to the target read address among the program addresses; and

controlling a read operation on the target read address according to whether a program operation on the program address corresponding to the target read address has been completed.

2. The method of claim 1, wherein the controlling of the read operation includes transmitting, when the program operation on the program address corresponding to the target read address is completed, a read command for the target read address to the memory device.

3. The method of claim 1, wherein the controlling of the read operation includes performing, when the program operation on the program address corresponding to the target read address is not completed, a barrier operation on the target read address.

4. The method of claim 3, further comprising:

checking a program progress state for a program address corresponding to the target read address on which the barrier operation is performed; and

transmitting to the memory device, when a program operation on the program address corresponding to the target read address on which the barrier operation is performed is completed, a read command for the target read address on which the barrier operation is performed.

5. The method of claim 1, further comprising:

transmitting to the memory device a command for requesting program progress state information on the plurality of program addresses; and

receiving the program progress state information on the plurality of program addresses from the memory device.

6. A memory controller comprising:

a host interface layer configured to receive a host program request and a host read request;

a flash translation layer configured to generate and output a program command and a plurality of program addresses in response to the host program request, check a program progress state for a program address corresponding to a target read address when the target read address corresponding to the host read request is included in the program addresses, and control a read operation on the target read address according to whether a program operation on the program address corresponding to the target read address has been completed; and

a flash interface layer configured to transmit a command and addresses, which are output from the flash translation layer, to a memory device.

7. The memory controller of claim 6, wherein the flash translation layer generates and outputs, when the program operation on the program address corresponding to the target read address is completed, a read command for the target read address.

8. The memory controller of claim 6, wherein the flash translation layer performs, when the program operation on the program address corresponding to the target read address is not completed, a barrier operation on the target read address.

9. The memory controller of claim 8, wherein the flash translation layer generates and outputs, when a program operation on a program address corresponding to the target read address on which the barrier operation is performed is completed, a read command for the target read address on which the barrier operation is performed.

10. The memory controller of claim 6, wherein the flash translation layer generates and outputs a command for requesting program progress state information on the plurality of program addresses, and receives the program progress state information on the plurality of program addresses from the memory device.

11. A memory controller comprising:

a first index storage configured to store an address at which a program operation is completed among a plurality of addresses corresponding to a host program request;

a second index storage configured to store a start address to be used in a next host program request; and

a host request processor configured to control a read operation corresponding to a host read request according to whether a target read address corresponding to the host read request is located between the address stored in the first index storage and the address stored in the second index storage.

12. The memory controller of claim 11, wherein the host request processor transmits, when the value of the target read address is equal to or less than the value of the address stored in the first index storage, a read command for the target read address to a memory device.

13. The memory controller of claim 11, wherein the host request processor delays, when the value of the target read address is greater than the value of the address stored in the first index storage and is less than the value of the address stored in the second index storage, generation of the read command for the target read address.

14. The memory controller of claim 11, wherein the host request processor receives program progress state information on the plurality of addresses from the memory device, and updates the address stored in the first index storage, based on the received program progress state information.

15. The memory controller of claim 11, wherein the host request processor transmits to the memory device a command for requesting the program progress state information on the plurality of addresses.