INTEGRATED CIRCUIT AND DATA PROCESSING SYSTEM SUPPORTING ATTACHMENT OF A REAL ADDRESS-AGNOSTIC ACCELERATOR

• US 20190332537A1
• Filed: 03/15/2019
• Published: 10/31/2019
• Est. Priority Date: 04/28/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: BLANER, BARTHOLOMEW, SIEGEL, MICHAEL S., STUECHELI, JEFFREY A., STARKE, WILLIAM J., VALK, KENNETH M., IRISH, JOHN D., ARIMILLI, LAKSHMINARAYANA
• Granted Patent: US 10,846,235 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors

Abstract

An integrated circuit for a coherent data processing system includes a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface. A request response identifies a target of a corresponding memory access request utilizing a host tag specifying an entry associated with the target in the real address-based directory.

Claims

1. An integrated circuit for a coherent data processing system including a system memory, the integrated circuit comprising:

a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system;

a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system;

a real address-based directory inclusive of contents of the accelerator cache, wherein the real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory; and

request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface, wherein a request response among the request responses identifies a target of a corresponding memory access request among the memory access requests utilizing a host tag specifying an entry associated with the target in the real address-based directory.

2. The integrated circuit of claim 1, wherein:

the real address-based directory is a set-associative cache directory; and

the host tag specifies the entry in the real address-based directory by entry number.

3. The integrated circuit of claim 2, wherein the host tag specifies the entry in the real address-based directory by congruence class and entry number.

4. The integrated circuit of claim 1, and further comprising:

a translation cache including translation entries that associate real addresses with effective addresses utilized by the accelerator unit; and

a translation unit that translates effective addresses of targets identified in memory access requests received via the second communication interface by reference to the translation cache.

5. The integrated circuit of claim 1, wherein the integrated circuit refrains from communicating real addresses with the accelerator unit via the second interface.

6. A system, comprising:

the integrated circuit of claim 1;

the accelerator unit coupled to the integrated circuit via the second communication interface, wherein;

the accelerator cache includes a cache array and an effective address-based directory of contents of the cache array; and

the accelerator unit includes a host tag data structure that maps each of a plurality of host tags to a respective one of a plurality of storage locations in the accelerator cache.

7. A method of data processing in a coherent data processing system including a system memory, the method comprising:

host attach logic communicating memory access requests with the coherent data processing system via a first communication interface;

the host attach logic communicating, via a second communication interface, memory access requests with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from the system memory;

the host attach logic recording, in a real address-based directory inclusive of contents of the accelerator cache, data from the system memory accessed by the accelerator unit, wherein the recording includes assigning entries in the real address-based directory based on real addresses utilized to identify storage locations in the system memory; and

the host attach logic communicating memory access requests and request responses with the accelerator unit via the second communication interface, wherein a request response among the request responses identifies a target of a corresponding memory access request among the memory access requests utilizing a host tag specifying an entry associated with the target in the real address-based directory.

8. The method of claim 7, wherein:

the real address-based directory is a set-associative cache directory; and

the host tag specifies the entry in the real address-based directory by entry number.

9. The method of claim 8, wherein the host tag specifies the entry in the real address-based directory by congruence class and entry number.

10. The method of claim 7, and further comprising:

the host attach logic maintaining a translation cache including translation entries that associate real addresses with effective addresses utilized by the accelerator unit; and

the host attach logic translating effective addresses of targets identified in memory access requests received via the second communication interface by reference to the translation cache.

11. The method of claim 7, and further comprising the host attach logic refraining from communicating real addresses with the accelerator unit via the second interface.

12. The method of claim 7, and further comprising:

the accelerator unit maintaining a host tag data structure that maps each of a plurality of host tags to a respective one of a plurality of storage locations in the accelerator cache.

13. A design structure tangibly embodied in a storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

host attach logic for a coherent data processing system including a system memory, the host attach logic including;

a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system;

a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system;

a real address-based directory inclusive of contents of the accelerator cache, wherein the real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory; and

request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface, wherein a request response among the request responses identifies a target of a corresponding memory access request among the memory access requests utilizing a host tag specifying an entry associated with the target in the real address-based directory.

14. The design structure of claim 13, wherein:

the real address-based directory is a set-associative cache directory; and

the host tag specifies the entry in the real address-based directory by entry number.

15. The design structure of claim 14, wherein the host tag specifies the entry in the real address-based directory by congruence class and entry number.

16. The design structure of claim 13, and further comprising:

a translation cache including translation entries that associate real addresses with effective addresses utilized by the accelerator unit; and

a translation unit that translates effective addresses of targets identified in memory access requests received via the second communication interface by reference to the translation cache.

17. The design structure of claim 13, wherein the integrated circuit refrains from communicating real addresses with the accelerator unit via the second interface.

18. The design structure of claim 13, and further comprising:

the accelerator unit coupled to the integrated circuit via the second communication interface, wherein;

the accelerator cache includes a cache array and an effective address-based directory of contents of the cache array; and

the accelerator unit includes a host tag data structure that maps each of a plurality of host tags to a respective one of a plurality of storage locations in the accelerator cache.

19. The design structure of claim 13, wherein the design structure comprises a hardware description language (HDL) design structure.