COMMAND PACKETS FOR THE DIRECT CONTROL OF NON-VOLATILE MEMORY CHANNELS WITHIN A SOLID STATE DRIVE

• US 20190332555A1
• Filed: 07/10/2019
• Published: 10/31/2019
• Est. Priority Date: 10/26/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: McVay, Jeffrey
• Granted Patent: US 11,169,939 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Apparatuses and methods for providing and intetpreting command packets for direct control of memory channels are disclosed herein. An example apparatus includes flash memories configured into channels and a controller coupled to the flash memories. The controller receives packets and interpret the packets based at least on a first protocol, and determines whether any packets are linked based on a link identifier included in a block of each packet. The controller arranges the subset of packets based on an index included in the block of each packet of the subset of packets, and the subset of packets are arranged in order based on the respective indexes. A target flash memory and a target channel are determined by the controller based on flash memory and channel identifiers included in the block of each of the packet of the subset of packets.

Claims

1. An apparatus, comprising:

a plurality of flash memories configured into a plurality of channels, wherein each of the plurality of channels includes one or more of the plurality of flash memories; and

a controller coupled to the plurality of flash memories and configured to receive a plurality of packets and interpret each packet of the plurality of packets based on a first protocol, wherein the controller is further configured to;

determine whether any packets of the plurality of packets are linked based on a link identifier included in a block of each packet, wherein a subset of packets of the plurality of packets are linked if they have the same link identifier;

arrange the subset of packets based on an index included in the block of each packet of the subset of packets, wherein the subset of packets are arranged in order based on the respective indexes;

determine a target flash memory and a target channel based on flash memory and channel identifiers included in the block of each of the packet of the subset of packets, wherein each packet of the subset of packets identifies the same target flash memory and the same target channel; and

provide data, address and control signals to the target flash memory based on interpreting the block of each packet of the plurality of packets based on a second protocol.

2. The apparatus of claim 1, wherein the controller comprises:

a frontend interface configured to interpret the plurality of packets based on the first protocol; and

a backend interface configured to interpret the block of each packet of the plurality of packets based on the second protocol.

3. The apparatus of claim 2, wherein the first protocol is the Non-Volatile Memory Express protocol, and the second protocol is the Open NAND Flash Interface protocol.

4. The apparatus of claim 1, wherein the block of each packet of the plurality of packets further includes a plurality of control identifiers and a plurality of command identifiers, wherein each of the plurality of control identifier are associated with a subset of command identifiers of the plurality of command identifiers, wherein each of the control identifiers determines a type of command for each of the associated subset of command identifiers.

5. The apparatus of claim 4, wherein a set of bits of each of the plurality of control identifiers determine a command type of a respective one of the associated subset of command identifiers.

6. The apparatus of claim 4, wherein the command types may be one of a second protocol command, a second protocol address, a second protocol data, and a user-defined command.

7. The apparatus of claim 1, wherein the block of each packet of the plurality of packets is a user-defined block of DWords of a Non-Volatile Memory Express submission queue entry.

8. An apparatus, comprising:

a plurality of flash memories configured into a plurality of channels, wherein each of the plurality of channels includes one or more of the plurality of flash memories; and

a controller, coupled to the plurality of flash memories, the controller comprising;

a frontend interface configured to receive a plurality of packets and interpret each of the plurality of packets based on a first protocol, and wherein the frontend interface is configured to link a subset of packets of the plurality of packets based on a link identifier included in a block of each packet of the subset of packets being the same, and order the subset of packets into an order based on an index identifier included in the block of each packet of the subset of packets, and determine a flash memory of the plurality of flash memories and a channel of the plurality of channels the subset of packets is directed toward, and further configured to provide at least the block of each of the subset of packets; and

a backend interface coupled to the frontend interface and the plurality of flash memories, the backend interface configured to receive at least the block of each of the subset of packets and interpret each block of the subset of packets based on a second protocol, and provide control signals, and operands to the flash memory of the plurality of flash memories over the channel of the plurality of channels.

9. The apparatus of claim 8, wherein the subset of packets is performed as a single command and a single notification is provided upon completion of the single command

10. The apparatus of claim 8, wherein the backend interface is configured to determine a type of control signal to provide for each operand based on an associated control identifier included m each block of each of the subset of packets.

11. The apparatus of claim 10, wherein the type of control signal is one of an address latch enable, and a command latch enable.

12. The apparatus of claim 8, wherein a type of opcode is one of a user-defined command, an Open NAND Flash Interface (ONFI) command, an ONFI address, and an ONFI data.

13. The apparatus of claim 12, wherein the ONFI address may comprise a physical address for a plurality of rows and a plurality of columns of the flash memory of the plurality of flash memories.

14. The apparatus of claim 8, wherein second protocol includes user-defined commands.

15. The apparatus of claim 8 wherein an operand type is determined by bits of an associated control byte included in each block of each of the linked subset of packets.

16. A method, comprising:

receiving a plurality of packets, wherein each packet includes at least two blocks;

interpreting a first block and at least a portion of a second block of each of the plurality of packets based on a first protocol;

based on the interpreting the at least a first portion of the second block of each of the plurality of packets, determining whether a subset of packets of the plurality of packets are linked based on a link identifier included in the first portion of the second block of each packet of the subset of packets;

based on determining that there is a subset of packets of the plurality of packets that are linked, ordering the subset of packets based on an index included in the first portion of the second block of each packet of the subset of packets;

interpreting a second portion of the second block of each packet of the subset of packets based on a second protocol;

providing control signals to a target flash memory of a plurality of flash memories of a target channel of a plurality of channels, wherein the target flash memory and the target channel is identified in the first portion of the second block of each packet of the subset of packets; and

providing operands to the target flash memory of the target, wherein the operands and a type of each operand are identified in the second portion of the second block of each packet of the subset of packets.

17. The method of claim 16, further including:

determining the type of operands based on respective bits of a control identifier associated with each operand, wherein the type of operands may be based on the second protocol.

18. The method of claim 16, further comprising:

determining the index of each packet of the subset of packets; and

placing the packets of the subset of packets in order of increasing index to form a single command; and

providing a completion notification based on performance of the single command.

19. The method of claim 16, wherein a block of the plurality of packets comprises a block including entries directed at the second protocol that provides low level flash memory control that the first protocol does not provide.

20. The method of claim 16, wherein a subset of packets of the plurality of packets are linked if the link identifier included in the first portion of the second block of each packet of the subset of packets is the same.