System and Method of Managing Signals in Information Handling Systems
First Claim
1. An information handling system, comprising:
- a processor;
a memory medium that stores information handling system firmware, executable by the processor, and that is coupled to the at least one processor;
a plurality of dies, each of the plurality of dies includes at least one processing core and at least one Peripheral Component Interconnect Express (PCIe) root complex;
a plurality of PCIe risers, each of the plurality of PCIe risers including a plurality of PCIe slots; and
circuitry that is coupled to the plurality of dies and coupled to the plurality of PCIe risers;
wherein the circuitry is configured to;
receive a first signal from the information handling system firmware executed by the processor;
provide, based at least on the first signal, each of a first plurality of reset assertion signals to each of the plurality of PCIe risers, respectively;
receive a second plurality of reset assertion signals from the plurality of dies, respectively;
receive a second signal from the information handling system firmware executed by the processor;
determine that the circuitry received the second plurality of reset assertion signals and the second signal; and
after determining that the circuitry received the second plurality of signals and the second signal, provide each of a third plurality of reset de-assertion signals to a respective PCIe riser of the plurality of PCIe risers.
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Accused Products
Abstract
In one or more embodiments, one or more systems, methods, and/or processes may receive a first signal from information handling system firmware; may provide, based at least on the first signal, each of first multiple reset assertion signals to each of respective multiple Peripheral Component Interconnect Express (PCIe) risers, each of the multiple PCIe risers including multiple PCIe slots; may receive second multiple reset assertion signals from respective multiple dies, each of the multiple dies includes at least one processing core and at least one PCIe root complex; may receive a second signal from the information handling system firmware; may determine that the second multiple reset assertion signals and the second signal were received; and may, after determining that the second multiple signals and the second signal were received, provide each of third multiple reset de-assertion signals to a respective PCIe riser of the multiple PCIe risers.
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Citations
20 Claims
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1. An information handling system, comprising:
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a processor; a memory medium that stores information handling system firmware, executable by the processor, and that is coupled to the at least one processor; a plurality of dies, each of the plurality of dies includes at least one processing core and at least one Peripheral Component Interconnect Express (PCIe) root complex; a plurality of PCIe risers, each of the plurality of PCIe risers including a plurality of PCIe slots; and circuitry that is coupled to the plurality of dies and coupled to the plurality of PCIe risers; wherein the circuitry is configured to; receive a first signal from the information handling system firmware executed by the processor; provide, based at least on the first signal, each of a first plurality of reset assertion signals to each of the plurality of PCIe risers, respectively; receive a second plurality of reset assertion signals from the plurality of dies, respectively; receive a second signal from the information handling system firmware executed by the processor; determine that the circuitry received the second plurality of reset assertion signals and the second signal; and after determining that the circuitry received the second plurality of signals and the second signal, provide each of a third plurality of reset de-assertion signals to a respective PCIe riser of the plurality of PCIe risers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method, comprising:
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circuitry, of an information handling system, receiving a first signal from information handling system firmware; the circuitry providing, based at least on the first signal, each of a first plurality of reset assertion signals to each of a respective plurality of Peripheral Component Interconnect Express (PCIe) risers, each of the plurality of PCIe risers including a plurality of PCIe slots; the circuitry receiving a second plurality of reset assertion signals from a respective plurality of dies, each of the plurality of dies includes at least one processing core and at least one PCIe root complex; the circuitry receiving a second signal from the information handling system firmware; the circuitry determining that the circuitry received the second plurality of reset assertion signals and the second signal; and after the circuitry determining that the circuitry received the second plurality of signals and the second signal, the circuitry providing each of a third plurality of reset de-assertion signals to a respective PCIe riser of the plurality of PCIe risers. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. Circuitry, configured to:
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receive a first signal from information handling system firmware; provide, based at least on the first signal, each of a first plurality of reset assertion signals to each of a respective plurality of Peripheral Component Interconnect Express (PCIe) risers, each of the plurality of PCIe risers including a plurality of PCIe slots; receive a second plurality of reset assertion signals from a respective plurality of dies, each of the plurality of dies includes at least one processing core and at least one PCIe root complex; receive a second signal from the information handling system firmware; determine that the circuitry received the second plurality of reset assertion signals and the second signal; and after determining that the circuitry received the second plurality of signals and the second signal, provide each of a third plurality of reset de-assertion signals to a respective PCIe riser of the plurality of PCIe risers. - View Dependent Claims (17, 18, 19, 20)
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Specification