SEMICONDUCTOR PROCESS MODELING TO ENABLE SKIP VIA IN PLACE AND ROUTE FLOW

• US 20190332738A1
• Filed: 04/25/2018
• Published: 10/31/2019
• Est. Priority Date: 04/25/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shao, Dongbing, Xu, Zheng, Clevenger, Lawrence A.
• Granted Patent: US 10,586,012 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

Claims

1. A method for incorporating skip vias in a place and route flow of an integrated circuit design, the method comprising:

employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer; and

when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

2. The method of claim 1, further comprising automatically adding the skip vias during the place and route flow.

3. The method of claim 1, further comprising adding the skip vias in a layer-by-layer fashion.

4. The method of claim 1, further comprising generating a list of failed skip vias.

5. The method of claim 1, wherein the place and route tool is a program that automates back end of the line (BEOL) wiring.

6. The method of claim 1, wherein the design rule includes width rules and minimum space rules.

7. A method for incorporating skip vias in a place and route flow of an integrated circuit design, the method comprising:

placing cells by employing a place and route tool;

selecting first metal layer pin access points for each first metal layer shape;

adding a skip via over the first metal layer;

adding a third metal layer over the skip via, the third metal layer connected to the first metal layer;

determining whether a violation of a design rule is triggered due to the addition of the skip via; and

if the violation of the design rule is confirmed, substituting the skip via with a standard via.

8. The method of claim 7, further comprising, if the violation of the design rule is confirmed, adding a second metal layer to connect the standard via between the first and second metals layers.

9. The method of claim 8, further comprising, determining whether the adding of the second metal layer triggers the violation of the design rule.

10. The method of claim 7, further comprising automatically adding the skip vias during the place and route flow.

11. The method of claim 7, further comprising adding the skip vias in a layer-by-layer fashion.

12. The method of claim 7, further comprising generating a list of failed skip vias.

13. The method of claim 7, wherein the place and route tool is a program that automates back end of the line (BEOL) wiring.

14. The method of claim 7, wherein the design rule includes width rules and minimum space rules.

15. A method for incorporating skip vias in a place and route flow of an integrated circuit design, the method comprising:

placing cells by employing a place and route tool;

creating a first metal layer pin connection list;

determining whether a skip via can land on one or more first metal layer pins;

if confirmed that the skip via can land on the one or more first metal layer pins, determining whether the first metal layer pins are from different cells; and

if the first metal layer pins are from different cells, adding a skip via.

16. The method of claim 15, further comprising automatically adding the skip vias during the place and route flow.

17. The method of claim 15, further comprising adding the skip vias in a layer-by-layer fashion.

18. The method of claim 15, further comprising generating a list of failed skip vias.

19. The method of claim 15, wherein the place and route tool is a program that automates back end of the line (BEOL) wiring.

20. The method of claim 15, wherein determining whether the skip via can land on the one or more first metal layer pins involves checking for design rule violations.