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SEMICONDUCTOR PROCESS MODELING TO ENABLE SKIP VIA IN PLACE AND ROUTE FLOW

  • US 20190332738A1
  • Filed: 04/25/2018
  • Published: 10/31/2019
  • Est. Priority Date: 04/25/2018
  • Status: Active Grant
First Claim
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1. A method for incorporating skip vias in a place and route flow of an integrated circuit design, the method comprising:

  • employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer; and

    when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

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