SEMICONDUCTOR MEMORY DEVICE

• US 20190333549A1
• Filed: 03/29/2019
• Published: 10/31/2019
• Est. Priority Date: 04/25/2018
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Okabe, Sho
• Granted Patent: US 11,056,154 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A semiconductor memory device for suppressing the peak current during the read operation is provided. A flash memory of the disclosure includes a memory cell array; a plurality of charge pump circuits; and a controller controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing.

Claims

1. A semiconductor memory device, comprising:

a memory cell array;

a plurality of charge pump circuits; and

a controller controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing.

2. The semiconductor memory device according to claim 1, wherein the controller controls the timing of activating the charge pump circuits when performing reading during a bit line precharge period.

3. The semiconductor memory device according to claim 1, wherein the controller shifts a timing of activating at least one charge pump circuit of the charge pump circuits.

4. The semiconductor memory device according to claim 1, wherein the controller activates a first charge pump circuit, which has been activated in response to a rising edge of a clock signal, in response to the rising edge of the clock signal.

5. The semiconductor memory device according to claim 4, wherein the controller activates a second charge pump circuit, which has been activated in response to a falling edge of a clock signal, in response to the falling edge of the clock signal.

6. The semiconductor memory device according to claim 1, wherein the controller activates a third charge pump circuit in response to an odd-numbered rising edge and activates a fourth charge pump circuit in response to an even-numbered falling edge.

7. The semiconductor memory device according to claim 1, wherein the charge pump circuits comprise a charge pump circuit that generates a pass voltage to be applied to a non-selected page.

8. The semiconductor memory device according to claim 1, wherein the charge pump circuits comprise a charge pump circuit that generates a drive voltage for driving a selected transistor that is for supplying a voltage to a bit line.

9. The semiconductor memory device according to claim 1, wherein the reading comprises verify-read during a program operation or an erase operation.

10. The semiconductor memory device according to claim 1, wherein the charge pump circuit comprises:

a pump circuit;

a generation circuit receiving a clock signal to generate a first clock signal and a fourth clock signal;

a first inverter receiving and inverting the first clock signal to generate a second clock signal; and

a second inverter receiving and inverting the fourth clock signal to generate a third clock signal,

wherein the first, second, third, and fourth clock signals are provided to the pump circuit.

11. The semiconductor memory device according to claim 10, wherein the generation circuit comprises:

a first AND gate using the clock signal and a first enable signal as input and using the clock signal as output; and

a second AND gate using the clock signal and a second enable signal as input and using the fourth clock signal as output,

wherein the first AND gate and the second AND gate are independently controlled by the first enable signal and the second enable signal respectively.

12. The semiconductor memory device according to claim 10, wherein a selection signal outputted by the controller serves as an enable signal of a comparator,

the comparator compares an output voltage of the pump circuit with a target voltage to generate a comparison result, and

an AND gate receives the comparison result to generate the clock signal.