SEMICONDUCTOR MEMORY DEVICE
First Claim
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1. A semiconductor memory device, comprising:
- a memory cell array;
a plurality of charge pump circuits; and
a controller controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing.
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Abstract
A semiconductor memory device for suppressing the peak current during the read operation is provided. A flash memory of the disclosure includes a memory cell array; a plurality of charge pump circuits; and a controller controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing.
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Citations
12 Claims
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1. A semiconductor memory device, comprising:
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a memory cell array; a plurality of charge pump circuits; and a controller controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification