SENSING A MEMORY CELL

• US 20190333562A1
• Filed: 04/25/2018
• Published: 10/31/2019
• Est. Priority Date: 04/25/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Vo, Huy T., El-Mansouri, Adam S., Tatapudi, Suryanarayana B., Porter, John D.
• Granted Patent: US 11,127,449 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2255 Bit-line or column circuits
• CPC Class Codes: G11C 11/2257 Word-line or row circuits
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

Claims

1. A device, comprising:

a memory cell configured to store a logic state;

a sense component configured to determine the logic state stored on the memory cell during a read operation; and

a circuit comprising a first switching component coupled with a first node and a second switching component coupled with the first switching component and the sense component, wherein a gate of the second switching component is coupled with the first node, the circuit configured to limit a voltage of a charge transferred between the memory cell and the sense component during the read operation.

2. The device of claim 1, wherein the first switching component is configured to selectively couple the sense component with the first node during the read operation based at least in part on the logic state stored on the memory cell.

3. The device of claim 2, wherein the first switching component is configured to selectively couple the sense component with the first node after the memory cell transfers a first charge indicative of a high logic state to the first node.

4. The device of claim 1, wherein the second switching component is configured to reduce the voltage associated with the charge for the sense component during the read operation.

5. The device of claim 1, wherein:

the first switching component comprises a p-type metal oxide semiconductor (PMOS) field effect transistor (FET) and the second switching component comprises an n-type metal oxide semiconductor (NMOS) field effect transistor (FET); and

the PMOS FET and the NMOS FET are arranged in a serial configuration.

6. The device of claim 5, wherein the PMOS FET is configured to selectively transfer, based at least in part on the logic state stored on the memory cell and a threshold voltage of the PMOS FET, the charge of the memory cell to the sense component in response to a second voltage being applied to a gate of the PMOS FET.

7. The device of claim 5, wherein:

the PMOS FET, based at least in part on a second voltage applied to a gate of the PMOS FET, is configured to be activated when a third voltage is present at the first node and not to be activated when a fourth voltage is present at the first node; and

the third voltage at the first node corresponds to a high logic state of the memory cell and the fourth voltage at the first node corresponds to a low logic state of the memory cell.

8. The device of claim 5, wherein:

the NMOS FET is configured as a source-follower to down convert the voltage associated with the charge to a second voltage that is within an operation voltage of the sense component; and

the second voltage is lower than the voltage associated with the charge by an amount corresponding to a threshold voltage of the NMOS FET.

9. The device of claim 1, wherein the circuit further comprises a third switching component coupled with the sense component and the second switching component, wherein the third switching component is configured to dampen a coupling noise between the sense component and the second switching component.

10. The device of claim 1, wherein the sense component is configured to operate at a first voltage that is lower than a second voltage at which the memory cell is configured to operate.

11. The device of claim 1, wherein:

the circuit is configured to couple the sense component with the memory cell when the memory cell transfers a first charge indicative of a high logic state to the first node during the read operation; and

the circuit is configured to isolate the sense component from the memory cell when the memory cell transfers a second charge indicative of a low logic state to the first node during the read operation.

12. A method, comprising:

precharging a digit line during a read operation;

activating a word line to couple a memory cell with the digit line after precharging the digit line;

transferring, based at least in part on activating the word line, a charge between the memory cell and a sense component through a circuit configured to reduce a voltage associated with the charge during the read operation; and

determining a logic state stored on the memory cell based at least in part on the charge transferred through the circuit.

13. The method of claim 12, further comprising:

biasing a gate of a first switching component of the circuit to a second voltage based at least in part on coupling the digit line with a first node.

14. The method of claim 13, further comprising:

activating the first switching component to couple the sense component with the first node based at least in part on biasing the gate of the first switching component to the second voltage when the memory cell stores a high logic state.

15. The method of claim 14, further comprising:

down converting, by a second switching component of the circuit, the voltage associated with the charge to a third voltage, wherein the third voltage is lower than the voltage associated with the charge by an amount corresponding to a threshold voltage of the second switching component.

16. The method of claim 13, further comprising:

maintaining the first switching component in a deactivated state when the gate of the first switching component is biased to the second voltage when the memory cell stores a low logic state.

17. The method of claim 12, wherein transferring the charge between the memory cell and the sense component through the circuit further comprises:

activating the circuit to couple the sense component with the memory cell when the memory cell transfers a first charge indicative of a high logic state to a first node during the read operation.

18. The method of claim 17, further comprising:

down converting a voltage associated with the first charge for the sense component based at least in part on activating the circuit to couple the sense component with the memory cell.

19. The method of claim 12, wherein determining the logic state stored on the memory cell further comprises:

comparing a reduced voltage associated with the charge transferred through the circuit with a reference voltage of the sense component.

20. The method of claim 12, further comprising:

precharging a first node to a first voltage based at least in part on precharging the digit line; and

isolating the digit line from the first node for a duration during the read operation based at least in part on precharging the first node to the first voltage, wherein activating the word line to couple the memory cell with the digit line is based at least in part on isolating the digit line from the first node.

21. The method of claim 20, further comprising:

recoupling the digit line with the first node after the duration during the read operation based at least in part on activating the word line, wherein transferring the charge between the memory cell and the sense component is based at least in part on recoupling the digit line with the first node.

22. The method of claim 12, further comprising:

coupling the digit line with a first node that has been precharged to a first voltage based at least in part on activating the word line, wherein transferring the charge between the memory cell and the sense component is based at least in part on coupling the digit line with the first node.

23. The method of claim 22, wherein coupling the digit line with the first node establishes the voltage at the first node indicative of the logic state stored on the memory cell.

24. The method of claim 12, further comprising:

activating the sense component based at least in part on transferring the charge between the memory cell and the sense component; and

establishing a second voltage at a second node associated with the sense component based at least in part on activating the sense component, wherein the second voltage is indicative of the logic state stored on the memory cell.

25. A memory device, comprising:

a memory array comprising a memory cell coupled with a digit line and a word line;

a controller coupled with the memory array, the controller being operable to;

precharge the digit line during a read operation;

activate the word line to couple the memory cell with the digit line after precharging the digit line;

transfer, based at least in part on activating the word line, a charge between the memory cell and a sense component through a circuit configured to reduce a voltage associated with the charge during the read operation; and

determine a logic state stored on the memory cell based at least in part on the charge transferred through the circuit.