SENSING A MEMORY CELL

• US 20190333563A1
• Filed: 04/25/2018
• Published: 10/31/2019
• Est. Priority Date: 04/25/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Di Vincenzo, Umberto
• Granted Patent: US 10,607,676 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2255 Bit-line or column circuits
• CPC Class Codes: G11C 11/2257 Word-line or row circuits
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/2293 Timing circuits or methods
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a cascode may couple a precharged capacitor with the memory cell to transfer a charge between the precharged capacitor and the memory cell. The cascode may isolate the capacitor from the memory cell based on the charge transferred between the capacitor and the memory cell. A second capacitor (e.g., a parasitic capacitor) may continue to provide an additional amount of charge to the memory cell during the read operation. Such a change in capacitance value during the read operation may provide a large sense window due to a non-linear voltage characteristics associated with the change in capacitance value.

Claims

1. A device, comprising:

a memory cell configured to store a logic state;

a capacitor configured to integrate a charge associated with the memory cell during a read operation;

a sense component configured to determine the logic state stored on the memory cell during the read operation;

a first cascode coupled with the memory cell and a first node;

a second cascode coupled with the capacitor and the first node; and

a transistor coupled with the first node and the sense component and configured to selectively couple the first node with the sense component during the read operation after the capacitor is isolated from the first node.

4. The device of claim 1, wherein the second cascode is configured to enable a sense window during the read operation based at least in part on the second cascode being coupled with the capacitor and the sense component.

5. The device of claim 1, further comprising:

a second transistor coupled with the capacitor and a second node of the second cascode, the second transistor is configured to precharge the capacitor to a first voltage during the read operation.

6. The device of claim 1, wherein the second cascode is configured to isolate the capacitor from the memory cell after transferring at least a portion of the charge to the memory cell during the read operation.

7. The device of claim 1, further comprising:

a second capacitor coupled with the first node, wherein the second capacitor is configured to transfer an additional charge to the memory cell after the capacitor is isolated from the memory cell.

8. The device of claim 7, wherein the second capacitor comprises a parasitic capacitance at the first node.

9. The device of claim 7, wherein at least the first node or the capacitor is configured to discharge a first voltage with a first rate of change during a first portion of the read operation.

10. The device of claim 9, wherein at least the first node or the second capacitor is configured to discharge a second voltage with a second rate of change during a second portion of the read operation when the memory cell stores a first logic state, wherein the second rate of change is greater than the first rate of change.

11. The device of claim 10, wherein the first rate of change and the second rate of change configure a sense window during the read operation.

12. The device of claim 1, wherein the memory cell is configured to receive, when the memory cell stores a first logic state, a first amount of charge during the read operation that is greater than a second amount of charge received when the memory cell stores a second logic state.

13. The device of claim 1, wherein:

the first cascode comprises an n-type metal oxide semiconductor (NMOS) field effect transistor (FET) and the second cascode comprises a p-type metal oxide semiconductor (PMOS) field effect transistors (FET).

14. The device of claim 1, wherein a value of a voltage source applied to a gate of the second cascode and a threshold voltage of the second cascode are configured to deactivate the second cascode when the charge has been transferred from the capacitor to the memory cell during the read operation.

2-3. -3. (canceled)

15. A method, comprising:

precharging a digit line to a first voltage;

precharging a capacitor to a second voltage, the capacitor being configured to integrate a charge associated with a memory cell during a read operation;

transferring the charge between the memory cell and the capacitor through a first cascode and a second cascode during the read operation, the first cascode being coupled with the memory cell and a first node associated with a sense component, and the second cascode being coupled with the capacitor and the first node;

isolating the first node from the capacitor based at least in part on transferring the charge;

coupling, using a transistor, the first node with the sense component after isolating the first node from the capacitor; and

determining a logic state stored on the memory cell based at least in part on coupling the first node with the sense component.

16. The method of claim 15, further comprising:

coupling the memory cell to the digit line that has been charged to the first voltage; and

supplying the charge from the capacitor to the memory cell through the first cascode and the second cascode based at least in part on coupling the memory cell to the digit line, wherein transferring the charge between the memory cell and the capacitor is based at least in part on supplying the charge.

17. The method of claim 16, wherein the charge supplied from the capacitor through the first cascode and the second cascode is associated with the memory cell storing a first logic state, the charge being less than a second charge associated with the memory cell storing a second logic state.

18. The method of claim 15, further comprising:

isolating the capacitor from the memory cell by deactivating the second cascode based at least in part on transferring the charge between the memory cell and the capacitor through the first cascode and the second cascode.

19. The method of claim 18, wherein deactivating the second cascode is based at least in part on a voltage across the capacitor being reduced during the read operation.

20. The method of claim 15, further comprising:

transferring an additional charge from the first node to the memory cell based at least in part on transferring the charge between the memory cell and the capacitor through the first cascode and the second cascode.

21. The method of claim 15, further comprising:

biasing a word line associated with the memory cell to couple the memory cell with the digit line based at least in part on precharging the digit line to the first voltage.

22. The method of claim 21, further comprising:

coupling the memory cell to the first node through the first cascode based at least in part on biasing the word line, wherein the first node is configured to couple with the sense component; and

establishing a voltage that is indicative of the logic state stored on the memory cell at the first node based at least in part on coupling the memory cell to the first node.

23. The method of claim 22, further comprising:

deactivating the second cascode to isolate the first node from the capacitor based at least in part on establishing the voltage at the first node; and

activating the transistor positioned between the first node and the sense component to couple the first node with the sense component during the read operation based at least in part on deactivating the first cascode.

24. The method of claim 23, further comprising:

comparing the voltage at the first node and a reference voltage associated with the sense component based at least in part on activating the transistor, wherein determining the logic state stored on the memory cell is based at least in part on comparing the voltage at the first node and the reference voltage.

25. A memory device, comprising:

a memory array comprising a memory cell coupled with a digit line;

a controller coupled with the memory array and with a capacitor configured to integrate a charge associated with the memory cell during a read operation, the controller configured to cause the memory device;

precharge the digit line to a first voltage;

precharge the capacitor to a second voltage;

transfer the charge between the memory cell and the capacitor through a first cascode and a second cascode during the read operation, the first cascode being coupled with the memory cell and a first node associated with a sense component, and the second cascode being coupled with the capacitor and the first node; and

isolate the first node from the capacitor based at least in part on transferring the charge;

couple, using a transistor, the first node with the sense component after isolating the first node from the capacitor; and

determine a logic state stored on the memory cell based at least in part on coupling the first node with the sense component.