METHOD FOR PROGRAMMING A RESISTIVE MEMORY

• US 20190333579A1
• Filed: 04/26/2019
• Published: 10/31/2019
• Est. Priority Date: 04/27/2018
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: GROSSI, Alessandro, VIANELLO, Elisa
• Granted Patent: US 10,839,902 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/005 Read using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure

Abstract

A method for programming a non-volatile resistive memory including a plurality of non-volatile resistive memory cells, each memory cell being able to switch in a reversible manner between a low resistance state in which the memory cell has an electrical resistance value lower than a first resistance threshold; and a high resistance state in which the memory cell has an electrical resistance value greater than the first resistance threshold; the programming method including determining the first resistance threshold carried out periodically during the lifetime of the resistive memory.

Claims

1. A method for programming a non-volatile resistive memory comprising a plurality of non-volatile resistive memory cells, each memory cell being able to switch in a reversible manner between:

a first programming state corresponding to a low resistance state, in which the memory cell has an electrical resistance value lower than a first resistance threshold; and

a second programming state corresponding to a high resistance state, in which the memory cell has an electrical resistance value greater than the first resistance threshold;

the programming method comprising determining the first resistance threshold carried out periodically, the determining comprising;

a first writing step intended to place a first group of memory cells in the low resistance state, a first number of memory cells of the first group not actually being placed in the low resistance state after the first programming step; and

a second erasing step intended to place a second group of memory cells in the high resistance state, a second number of memory cells of the second group not actually being placed in the high resistance state after the second programming step;

the first resistance threshold being determined so as to minimise a number of programming errors equal to a sum of the first number of memory cells and the second number of memory cells.

2. The programming method according to claim 1, wherein the determining of the first resistance threshold comprises:

a) defining a variable resistance threshold equal to the first resistance threshold determined during a preceding determination step;

b) carrying out the first writing step and the second erasing step using the variable resistance threshold;

c) determining the number of programming errors arising during step b);

d) repeating steps b) and c) after having modified the variable resistance threshold according to a predetermined sense of variation, steps b) and c) being repeated at least once and as long as the number of programming errors decreases between two consecutive steps b);

e) defining the first resistance threshold equal to the variable resistance threshold used during the penultimate step b).

3. The programming method according to claim 1, wherein two consecutive steps of determining the first resistance threshold are separated by a time interval corresponding to a first predetermined number of programming cycles that at least one memory cell has undergone.

4. The programming method according to claim 1, further comprising a programming step comprising at least one of:

a writing step intended to place at least one memory cell in the low resistance state, said at least one memory cell being considered as being in the low resistance state at the end of the writing step if the resistance value of said at least one memory cell is lower than a second resistance threshold lower than or equal to the first resistance threshold;

an erasing step intended to place at least one memory cell in the high resistance state, said at least one memory cell being considered as being in the high resistance state at the end of the erasing step if the resistance value of said at least one memory cell is greater than a third resistance threshold greater than or equal to the first resistance threshold;

the second resistance threshold and the third resistance threshold being defined as a function of the determined first resistance threshold.

5. The programming method according to claim 4, wherein the second resistance threshold and the third resistance threshold are equal to the first resistance threshold.

6. The programming method according to claim 4, wherein the second resistance threshold and the third resistance threshold are respectively equal to 90% and to 110% of the first resistance threshold.

7. The programming method according to claim 1, wherein each memory cell comprises a dielectric material arranged between two electrodes, the memory cell passing from the high resistance state to the low resistance state when a switching zone is formed in the dielectric material, the switching zone electrically connecting the electrodes of the memory cell, the programming method further comprising a step of initialisation of the resistive memory comprising:

forming for the first time the switching zone of each memory cell; and

conditioning the memory cells by repeating a second predetermined number of programming cycles each comprising an operation of writing and an operation of erasing the memory cells.

8. The programming method according to claim 1, wherein the memory cells are of CBRAM or OxRAM type.