SHIFT REGISTER, DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE

• US 20190333597A1
• Filed: 01/08/2019
• Published: 10/31/2019
• Est. Priority Date: 04/26/2018
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: LIU, Peng, Fan, Jun, Liu, Yusheng, Liu, Bailing, Zhang, Han, Wang, Zhen, Qiao, Yun, Wang, Zhengkui, Cong, Lele, Li, Mei
• Granted Patent: US 10,930,360 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers

Abstract

A shift register includes a first input sub-circuit configured to transfer a first input signal at a first input terminal to a first node in response to a first scan signal at a first scan terminal being active, a first level control sub-circuit configured to transfer a first power supply voltage at a first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential, and an output sub-circuit configured to transfer a first clock signal at a first clock terminal to a first output in response to the first output control node being at an active potential, and to transfer a second clock signal at a second clock terminal to a second output terminal in response to the second output control node being at an active potential.

Claims

1. A shift register, comprising:

a first scan terminal configured to receive a first scan signal;

a first input terminal configured to receive a first input signal;

a first power supply terminal configured to receive a first power supply voltage;

a second power supply terminal configured to receive a second power supply voltage;

a first clock terminal configured to receive a first clock signal;

a second clock terminal configured to receive a second clock signal;

a first output terminal configured to output a first output signal;

a second output terminal configured to output a second output signal;

a first input sub-circuit configured to transfer the first input signal at the first input terminal to a first node in response to the first scan signal at the first scan terminal being active;

a first level control sub-circuit configured to transfer the first power supply voltage at the first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential; and

an output sub-circuit configured to transfer the first clock signal at the first clock terminal to the first output terminal as the first output signal in response to the first output control node being at an active potential, and configured to transfer the second clock signal at the second clock terminal to the second output terminal as the second output signal in response to the second output control node being at an active potential.

2. The shift register of claim 1, further comprising:

a third clock terminal configured to receive a third clock signal;

a reset terminal configured to receive a reset signal;

a second level control sub-circuit configured to transfer the third clock signal at the third clock terminal to a third node in response to the first scan signal at the first scan terminal being active;

a third level control sub-circuit configured to transfer the first power supply voltage at the first power supply terminal to a third output control node in response to the third node being at an active potential, and configured to transfer the second power supply voltage at the second power supply terminal to the third output control node in response to the first node being at an active potential; and

a reset sub-circuit configured to transfer the reset signal at the reset terminal to the third output control node in response to the reset signal at the reset terminal being active, and configured to transfer the second power supply voltage at the second supply terminal to the second node, the first output terminal, and the second output terminal in response to the third output control node being at an active potential.

3. The shift register of claim 2, further comprising:

a second scan terminal configured to receive a second scan signal;

a second input terminal configured to receive a second input signal;

a fourth clock terminal configured to receive a fourth clock signal;

a second input sub-circuit configured to transfer the second input signal at the second input terminal to the first node in response to the second scan signal at the second scan terminal being active; and

a fourth level control sub-circuit configured to transfer the fourth clock signal at the fourth clock terminal to the third node in response to the second scan signal at the second scan terminal being active.

4. The shift register of claim 1,

wherein the first input sub-circuit comprises a first transistor comprising a control electrode connected to the first scan terminal, a first electrode connected to the first input terminal, and a second electrode connected to the first node,

wherein the first level control sub-circuit comprises:

a second transistor comprising a control electrode connected to the first node, a first electrode connected to the first power supply terminal, and a second electrode connected to the second node;

a third transistor comprising a control electrode connected to the first power supply terminal, a first electrode connected to the second node, and a second electrode connected to the first output control node;

a fourth transistor comprising a control electrode connected to the first power supply terminal, a first electrode connected to the second node, and a second electrode connected to the second output control node;

a first capacitor comprising a first terminal connected to the second node and a second terminal connected to the second power supply terminal, and

wherein the output sub-circuit comprises;

a fifth transistor comprising a control electrode connected to the first output control node, a first electrode connected to the first clock terminal, and a second electrode connected to the first output terminal; and

a sixth transistor comprising a control electrode connected to the second output control node, a first electrode connected to the second clock terminal, and a second electrode connected to the second output terminal.

5. The shift register of claim 2,

wherein the second level control sub-circuit comprises a seventh transistor comprising a control electrode connected to the first scan terminal, a first electrode connected to the third clock terminal, and a second electrode connected to the third node,

wherein the third level control sub-circuit comprises:

an eighth transistor comprising a control electrode connected to the third node, a first electrode connected to the first power supply terminal, and a second electrode connected to the third output control node;

a ninth transistor comprising a control electrode connected to the first node, a first electrode connected to the third output control node, and a second electrode connected to the second power supply terminal; and

a second capacitor comprising a first terminal connected to the third output control node and a second terminal connected to the second power supply terminal, and

wherein the reset sub-circuit comprises;

a tenth transistor comprising a control electrode connected to the third output control node, a first electrode connected to the second node, and a second electrode connected to the second power supply terminal;

an eleventh transistor comprising a control electrode connected to the third output control node, a first electrode connected to the first output terminal, and a second electrode connected to the second power supply terminal;

a twelfth transistor comprising a control electrode connected to the third output control node, a first electrode connected to the second output terminal, and a second electrode connected to the second power supply terminal; and

a thirteenth transistor comprising a control electrode connected to the reset terminal, a first electrode connected to the reset terminal, and a second electrode connected to the third output control node.

6. The shift register of claim 3,

wherein the second input sub-circuit comprises a fourteenth transistor comprising a control electrode connected to the second scan terminal, a first electrode connected to the first node, and a second electrode connected to the second input terminal, and

wherein the fourth level control sub-circuit comprises a fifteenth transistor comprising a control electrode connected to the second scan terminal, a first electrode connected to the third node, and a second electrode connected to the fourth clock terminal.

7. The shift register of claim 3, further comprising:

a first control terminal configured to receive a first control signal;

a second control terminal configured to receive a second control signal;

a touch control sub-circuit configured to transfer the second power supply voltage at the second power supply terminal to the first output terminal and the second output terminal in response to the first control signal at the first control terminal being active; and

a display control sub-circuit configured to transfer the second control signal at the second control terminal to the first output terminal and the second output terminal in response to the second control signal at the second control terminal being active.

8. The shift register of claim 7,

wherein the touch control sub-circuit comprises a sixteenth transistor comprising a control electrode connected to the first control terminal, a first electrode connected to the second power supply terminal, and a second electrode connected to the first output terminal and the second output terminal;

and

wherein the display control sub-circuit comprises a seventeenth transistor comprising a control electrode connected to the second control terminal, a first electrode connected to the second control terminal, and a second electrode connected to the first output terminal and the second output terminal.

9. The shift register of claim 8,

wherein the first input sub-circuit comprises a first transistor comprising a control electrode connected to the first scan terminal, a first electrode connected to the first input terminal, and a second electrode connected to the first node,

wherein the first level control sub-circuit comprises:

a second transistor comprising a control electrode connected to the first node, a first electrode connected to the first power supply terminal, and a second electrode connected to the second node;

a third transistor comprising a control electrode connected to the first power supply terminal, a first electrode connected to the second node, and a second electrode connected to the first output control node;

a fourth transistor comprising a control electrode connected to the first power supply terminal, a first electrode connected to the second node, and a second electrode connected to the second output control node; and

a first capacitor comprising a first terminal connected to the second node and a second terminal connected to the second power supply terminal,

wherein the output sub-circuit comprises;

a fifth transistor comprising a control electrode connected to the first output control node, a first electrode connected to the first clock terminal, and a second electrode connected to the first output terminal; and

a sixth transistor comprising a control electrode connected to the second output control node, a first electrode connected to the second clock terminal, and a second electrode connected to the second output terminal,

wherein the second level control sub-circuit comprises a seventh transistor comprising a control electrode connected to the first scan terminal, a first electrode connected to the third clock terminal, and a second electrode connected to the third node,

wherein the third level control sub-circuit comprises;

an eighth transistor comprising a control electrode connected to the third node, a first electrode connected to the first power supply terminal, and a second electrode connected to the third output control node;

a ninth transistor comprising a control electrode connected to the first node, a first electrode connected to the third output control node, and a second electrode connected to the second power supply terminal; and

a second capacitor comprising a first terminal connected to the third output control node and a second terminal connected to the second power supply terminal,

wherein the reset sub-circuit comprises;

a tenth transistor comprising a control electrode connected to the third output control node, a first electrode connected to the second node, and a second electrode connected to the second power supply terminal;

an eleventh transistor comprising a control electrode connected to the third output control node, a first electrode connected to the first output terminal, and a second electrode connected to the second power supply terminal;

a twelfth transistor comprising a control electrode connected to the third output control node, a first electrode connected to the second output terminal, and a second electrode connected to the second power supply terminal; and

a thirteenth transistor comprising a control electrode connected to the reset terminal, a first electrode connected to the reset terminal, and a second electrode connected to the third output control node,

wherein the second input sub-circuit comprises a fourteenth transistor comprising a control electrode connected to the second scan terminal, a first electrode connected to the first node, and a second electrode connected to the second input terminal, and

wherein the fourth level control sub-circuit comprises a fifteenth transistor comprising a control electrode connected to the second scan terminal, a first electrode connected to the third node, and a second electrode connected to the fourth clock terminal.

10. A gate driving circuit, comprising:

N cascaded shift registers of claim 3, wherein N is a positive integer and N≥

4,

wherein the first input terminal of a first one of the N cascaded shift registers or the second input terminal of an N-th one of the N cascaded shift registers is configured to receive a start signal,

wherein the second output terminal of a k-th one of the N cascaded shift registers is connected to the first input terminal of a (k+1)-th one of the N cascaded shift registers, k being a positive integer and 1≤

k<

N, and

wherein the first output terminal of the (k+1)-th shift register is connected to the second input terminal of the k-th shift register.

11. The gate driving circuit of claim 10,

wherein the first clock terminals of the N cascaded shift registers are configured to receive a same first clock signal,

wherein the second clock terminals of the N cascaded shift registers are configured to receive a same second clock signal,

wherein the third clock terminals of the N cascaded shift registers are configured to receive a same third clock signal, and

wherein the fourth clock terminals of the N cascaded shift registers are configured to receive a same fourth clock signal.

12. The gate driving circuit of claim 10,

wherein the first input sub-circuit comprises a first transistor comprising a control electrode connected to the first scan terminal, a first electrode connected to the first input terminal, and a second electrode connected to the first node,

wherein the first level control sub-circuit comprises:

a second transistor comprising a control electrode connected to the first node, a first electrode connected to the first power supply terminal, and a second electrode connected to the second node;

a third transistor comprising a control electrode connected to the first power supply terminal, a first electrode connected to the second node, and a second electrode connected to the first output control node;

a fourth transistor comprising a control electrode connected to the first power supply terminal, a first electrode connected to the second node, and a second electrode connected to the second output control node;

a first capacitor comprising a first terminal connected to the second node and a second terminal connected to the second power supply terminal, and

wherein the output sub-circuit comprises;

a fifth transistor comprising a control electrode connected to the first output control node, a first electrode connected to the first clock terminal, and a second electrode connected to the first output terminal; and

a sixth transistor comprising a control electrode connected to the second output control node, a first electrode connected to the second clock terminal, and a second electrode connected to the second output terminal.

13. The gate driving circuit of claim 10,

wherein the second level control sub-circuit comprises a seventh transistor comprising a control electrode connected to the first scan terminal, a first electrode connected to the third clock terminal, and a second electrode connected to the third node,

wherein the third level control sub-circuit comprises:

an eighth transistor comprising a control electrode connected to the third node, a first electrode connected to the first power supply terminal, and a second electrode connected to the third output control node;

a ninth transistor comprising a control electrode connected to the first node, a first electrode connected to the third output control node, and a second electrode connected to the second power supply terminal; and

a second capacitor comprising a first terminal connected to the third output control node and a second terminal connected to the second power supply terminal, and

wherein the reset sub-circuit comprises;

a tenth transistor comprising a control electrode connected to the third output control node, a first electrode connected to the second node, and a second electrode connected to the second power supply terminal;

an eleventh transistor comprising a control electrode connected to the third output control node, a first electrode connected to the first output terminal, and a second electrode connected to the second power supply terminal;

a twelfth transistor comprising a control electrode connected to the third output control node, a first electrode connected to the second output terminal, and a second electrode connected to the second power supply terminal; and

a thirteenth transistor comprising a control electrode connected to the reset terminal, a first electrode connected to the reset terminal, and a second electrode connected to the third output control node.

14. The gate driving circuit of claim 10,

wherein the second input sub-circuit comprises a fourteenth transistor comprising a control electrode connected to the second scan terminal, a first electrode connected to the first node, and a second electrode connected to the second input terminal, and

wherein the fourth level control sub-circuit comprises a fifteenth transistor comprising a control electrode connected to the second scan terminal, a first electrode connected to the third node, and a second electrode connected to the fourth clock terminal.

19. A display device comprising the gate driving circuit of claim 10.

20. The display device of claim 19,

wherein the first clock terminals of the N cascaded shift registers are configured to receive a same first clock signal,

wherein the second clock terminals of the N cascaded shift registers are configured to receive a same second clock signal,

wherein the third clock terminals of the N cascaded shift registers are configured to receive a same third clock signal, and

wherein the fourth clock terminals of the N cascaded shift registers are configured to receive a same fourth clock signal.

15. A method of driving a shift register, wherein the shift register comprises:

a first scan terminal configured to receive a first scan signal;

a second scan terminal configured to receive a second scan signal;

a first input terminal configured to receive a first input signal;

a second input terminal configured to receive a second input signal;

a first power supply terminal configured to receive a first power supply voltage;

a second power supply terminal configured to receive a second a power supply voltage;

a first clock terminal configured to receive a first clock signal;

a second clock terminal configured to receive a second clock signal;

a third clock terminal configured to receive a third clock signal;

a fourth clock terminal configured to receive a fourth clock signal;

a first output terminal configured to output a first output signal;

a second output terminal configured to output a second output signal;

a reset terminal configured to receive a reset signal;

a first input sub-circuit;

a first level control sub-circuit;

an output sub-circuit;

a second level control sub-circuit;

a third level control sub-circuit;

a reset sub-circuit; and

a second input sub-circuit, the method comprising;

at an input phase, transferring, by one of the first input sub-circuit and the second input sub-circuit, an input signal to a first node, and transferring, by the first level control sub-circuit, the first power supply voltage at the first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential; and

at an output phase subsequent to the input phase, transferring, by the output sub-circuit, the first clock signal at the first clock terminal to the first output terminal as the first output signal in response to the first output control node being at an active potential, and transferring, by the output sub-circuit, the second clock signal at the second clock terminal to the second output terminal as the second output signal in response to the second output control node being at an active potential.

16. The method of claim 15, further comprising:

at an initialization phase prior to the input phase, transferring, by the reset sub-circuit, the reset signal at the reset terminal to a third output control node in response to the reset signal at the reset terminal being active, and transferring, by the reset sub-circuit, the second power supply voltage at the second power supply terminal to a second node, the first output terminal and the second output terminal in response to the third output control node being at an active potential; and

at a hold phase subsequent to the output phase, transferring, by the second level control sub-circuit, the third clock signal at the third clock terminal to a third node in response to the first scan signal at the first scan terminal being active, transferring, by the third level control sub-circuit, the first power supply voltage at the first power supply terminal to the third output control node in response to the third node being at an active potential, transferring, by the third level control sub-circuit, the second power supply voltage at the second power supply terminal to the third output control node in response to the first node being at an active potential, and transferring, by the reset sub-circuit, the second power supply voltage at the second power supply terminal to the second node, the first output terminal, and the second output terminal in response to the third output control node being at an active potential.

17. The method of claim 15, wherein the shift register further comprises:

a first control terminal configured to receive a first control signal; and

a second control terminal configured to receive a second control signal;

a touch control sub-circuit; and

a display control sub-circuit, the method further comprising;

transferring, by the touch control sub-circuit, the second power supply voltage at the second power supply terminal to the first output terminal and the second output terminal, in response to the first control signal at the first control terminal being active; and

transferring, by the display control sub-circuit, the second control signal at the second control terminal to the first output terminal and the second output terminal, in response to the second control signal at the second control terminal being active.

18. The method of claim 15, wherein the transferring the input signal to the first node at the input phase comprises:

transferring, by the first input sub-circuit, the first input signal at the first input terminal to the first node in response to the shift register being in a forward scan mode in which the first scan signal is active; and

transferring, by the second input sub-circuit, the second input signal at the second input terminal to the first node in response to the shift register being in a reverse scan mode in which the second scan signal is active.