SHIFT REGISTER, DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE
First Claim
1. A shift register, comprising:
- a first scan terminal configured to receive a first scan signal;
a first input terminal configured to receive a first input signal;
a first power supply terminal configured to receive a first power supply voltage;
a second power supply terminal configured to receive a second power supply voltage;
a first clock terminal configured to receive a first clock signal;
a second clock terminal configured to receive a second clock signal;
a first output terminal configured to output a first output signal;
a second output terminal configured to output a second output signal;
a first input sub-circuit configured to transfer the first input signal at the first input terminal to a first node in response to the first scan signal at the first scan terminal being active;
a first level control sub-circuit configured to transfer the first power supply voltage at the first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential; and
an output sub-circuit configured to transfer the first clock signal at the first clock terminal to the first output terminal as the first output signal in response to the first output control node being at an active potential, and configured to transfer the second clock signal at the second clock terminal to the second output terminal as the second output signal in response to the second output control node being at an active potential.
1 Assignment
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Accused Products
Abstract
A shift register includes a first input sub-circuit configured to transfer a first input signal at a first input terminal to a first node in response to a first scan signal at a first scan terminal being active, a first level control sub-circuit configured to transfer a first power supply voltage at a first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential, and an output sub-circuit configured to transfer a first clock signal at a first clock terminal to a first output in response to the first output control node being at an active potential, and to transfer a second clock signal at a second clock terminal to a second output terminal in response to the second output control node being at an active potential.
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Citations
20 Claims
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1. A shift register, comprising:
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a first scan terminal configured to receive a first scan signal; a first input terminal configured to receive a first input signal; a first power supply terminal configured to receive a first power supply voltage; a second power supply terminal configured to receive a second power supply voltage; a first clock terminal configured to receive a first clock signal; a second clock terminal configured to receive a second clock signal; a first output terminal configured to output a first output signal; a second output terminal configured to output a second output signal; a first input sub-circuit configured to transfer the first input signal at the first input terminal to a first node in response to the first scan signal at the first scan terminal being active; a first level control sub-circuit configured to transfer the first power supply voltage at the first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential; and an output sub-circuit configured to transfer the first clock signal at the first clock terminal to the first output terminal as the first output signal in response to the first output control node being at an active potential, and configured to transfer the second clock signal at the second clock terminal to the second output terminal as the second output signal in response to the second output control node being at an active potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 19, 20)
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15. A method of driving a shift register, wherein the shift register comprises:
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a first scan terminal configured to receive a first scan signal; a second scan terminal configured to receive a second scan signal; a first input terminal configured to receive a first input signal; a second input terminal configured to receive a second input signal; a first power supply terminal configured to receive a first power supply voltage; a second power supply terminal configured to receive a second a power supply voltage; a first clock terminal configured to receive a first clock signal; a second clock terminal configured to receive a second clock signal; a third clock terminal configured to receive a third clock signal; a fourth clock terminal configured to receive a fourth clock signal; a first output terminal configured to output a first output signal; a second output terminal configured to output a second output signal; a reset terminal configured to receive a reset signal; a first input sub-circuit;
a first level control sub-circuit;an output sub-circuit;
a second level control sub-circuit;a third level control sub-circuit; a reset sub-circuit; and a second input sub-circuit, the method comprising; at an input phase, transferring, by one of the first input sub-circuit and the second input sub-circuit, an input signal to a first node, and transferring, by the first level control sub-circuit, the first power supply voltage at the first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential; and at an output phase subsequent to the input phase, transferring, by the output sub-circuit, the first clock signal at the first clock terminal to the first output terminal as the first output signal in response to the first output control node being at an active potential, and transferring, by the output sub-circuit, the second clock signal at the second clock terminal to the second output terminal as the second output signal in response to the second output control node being at an active potential. - View Dependent Claims (16, 17, 18)
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Specification