DATA STORAGE DEVICE WITH SELECTIVE CONNECTION TO NON-VOLATILE MEMORIES

• US 20190339880A1
• Filed: 05/02/2018
• Published: 11/07/2019
• Est. Priority Date: 05/02/2018
• Status: Active Grant

• Current Assignee: InnoGrit Technologies Co., Ltd.
• Original Assignee: Nyquist Semiconductor Limited
• Inventors: Jiang, Wei, Chen, Jie, Chien, Chiahung, Chen, Lin, Wu, Zining
• Granted Patent: US 10,564,858 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]

Abstract

An apparatus includes: a first memory controller that corresponds with a first type of non-volatile memory device; a second memory controller that corresponds to a second type of non-volatile memory device, wherein the second type of non-volatile memory device is different from the first type of non-volatile memory device; an physical layer (PHY) interface; and an interface controller coupled to the PHY interface for controlling signal transmission by the PHY interface; wherein the PHY interface is selectively configurable or is user-configured to allow the PHY interface to communicate with one or more memory devices belonging to the first type, the second type, or both.

Claims

1. An apparatus comprising:

a first memory controller that corresponds with a first type of non-volatile memory device;

a second memory controller that corresponds to a second type of non-volatile memory device, wherein the second type of non-volatile memory device is different from the first type of non-volatile memory device;

an physical layer (PHY) interface; and

an interface controller coupled to the PHY interface for controlling signal transmission by the PHY interface;

wherein the PHY interface is selectively configurable or is user-configured to allow the PHY interface to communicate with one or more memory devices belonging to the first type, the second type, or both;

wherein both the first memory controller corresponding with the first type of non-volatile memory device and the second memory controller corresponding with the second type of non-volatile memory device are implemented on a same chip, and wherein the first memory controller and the second memory controller are different from each other.

2. The apparatus of claim 1, wherein the PHY interface comprises pins that are selectively assignable or selectively assigned to operate as a type of pin specific to the first type of non-volatile memory device, or to the second type of non-volatile memory device.

3. The apparatus of claim 1, wherein the PHY interface comprises registers configured to allow functionalities of pins of the PHY interface to be programmed.

4. The apparatus of claim 1, wherein the interface controller is configured to control the signal transmission by the PHY interface based on a manner in which pins of the PHY interface is configured.

5. The apparatus of claim 1, further comprising a switch or a multiplexer coupled to the interface controller, wherein the interface controller is configured to control the switch or the multiplexer.

6. The apparatus of claim 1, wherein the first type of non-volatile memory device is a NAND memory device.

7. The apparatus of claim 1, wherein the second type of non-volatile memory device is a 3D XPoint memory device.

8. The apparatus of claim 1, wherein the PHY interface comprises a plurality of channels that are selectively configurable or configured.

9. The apparatus of claim 1, wherein the first memory controller, the second memory controller, and the PHY interface are integrated into an integrated circuit (IC) chip.

10. The apparatus of claim 1, wherein the one or more memory devices comprise a 3D XPoint memory device, a NAND memory device, or both.

11. A system comprising the apparatus of claim 1, and the one or more memory devices.

12. The system of claim 11, wherein the one or more memory devices comprise a 3D XPoint memory device, a NAND memory device, or both.

13. The system of claim 11, wherein the one or more memory devices are connected to the PHY interface via electrical connections.

34. The apparatus of claim 1, wherein a physical configuration of the PHY interface remains the same regardless of whether a first memory device belonging to the first type, or a second memory device belonging to the second type, is connected with the PHY interface, the first memory device and the second memory device having different respective interface connections.

14. An apparatus comprising:

a first memory controller that corresponds with a first type of non-volatile memory device;

a second memory controller that corresponds to a second type of non-volatile memory device, wherein the second type of non-volatile memory device is different from the first type of non-volatile memory device;

an physical layer (PHY) interface; and

an interface controller coupled to the PHY interface for controlling signal transmission by the PHY interface;

wherein the interface controller is configured to control signal transmission by the PHY interface based on a manner in which pins of the PHY interface is configured by a user;

wherein both the first memory controller corresponding with the first type of non-volatile memory device and the second memory controller corresponding with the second type of non-volatile memory device are implemented on a same chip, and wherein the first memory controller and the second memory controller are different from each other.

15. The apparatus of claim 14, wherein the PHY interface comprises pins that are selectively assignable or selectively assigned to operate as a type of pin specific to the first type of non-volatile memory device, or to the second type of non-volatile memory device.

16. The apparatus of claim 14, wherein the PHY interface comprises registers configured to allow functionalities of pins of the PHY interface to be programmed.

17. The apparatus of claim 14, further comprising a switch or a multiplexer coupled to the interface controller, wherein the interface controller is configured to control the switch or the multiplexer.

18. The apparatus of claim 14, wherein the first type of non-volatile memory device is a NAND memory device.

19. The apparatus of claim 14, wherein the second type of non-volatile memory device is a 3D XPoint memory device.

20. The apparatus of claim 14, wherein the PHY interface comprises a plurality of channels that are selectively configurable or configured.

21. The apparatus of claim 14, wherein the first memory controller, the second memory controller, and the PHY interface are integrated into an integrated circuit (IC) chip.

22. The apparatus of claim 14, wherein the pins of the PHY interface is configured by the user to communicate with one or more memory devices.

23. The apparatus of claim 22, wherein the one or more memory devices comprise a 3D XPoint memory device, a NAND memory device, or both.

24. A system comprising the apparatus of claim 22, and the one or more memory devices.

25. The system of claim 24, wherein the one or more memory devices comprise a 3D XPoint memory device, a NAND memory device, or both.

26. The system of claim 24, wherein the one or more memory devices are connected to the PHY interface via electrical connections.

35. The apparatus of claim 14, wherein a physical configuration of the PHY interface remains the same regardless of whether a first memory device belonging to the first type, or a second memory device belonging to the second type, is connected with the PHY interface, the first memory device and the second memory device having different respective interface connections.

27. A method performed by an apparatus, comprising:

receiving an electronic signal from a memory controller;

determining a signal type for the electronic signal;

determining one or more pins of a physical layer (PHY) interface of the apparatus that are assigned to receive the electronic signal based on the determined signal type; and

passing the electronic signal to the one or more pins of the PHY interface, wherein the PHY interface is designed to be physically connectable with different types of memory devices;

wherein the memory controller is a part of the apparatus that also includes an additional memory controller, and wherein the memory controller and the additional memory controller are different from each other.

28. The method of claim 27, wherein the electronic signal comprises a read command or a write command.

29. The method of claim 27, wherein the act of determining the one or more pins comprises determining a channel associated with the PHY interface that is assigned to implement a certain type of pin function for one of the types of memory devices, wherein the one or more pins belong to the channel.

30. The method of claim 27, wherein the electronic signal is for communication with a non-volatile memory device.

31. The method of claim 30, wherein the non-volatile memory device comprises a NAND memory device or a 3D XPoint memory device.

32. An apparatus comprising:

a first memory controller that corresponds with a first type of non-volatile memory device;

a second memory controller that corresponds to a second type of non-volatile memory device, wherein the second type of non-volatile memory device is different from the first type of non-volatile memory device;

an physical layer (PHY) interface; and

an interface controller coupled to the PHY interface for controlling signal transmission by the PHY interface;

wherein the PHY interface is selectively configurable or is user-configured to allow the PHY interface to communicate with one or more memory devices belonging to the first type, the second type, or both;

wherein both the first memory controller corresponding with the first type of non-volatile memory device and the second memory controller corresponding with the second type of non-volatile memory device are implemented on a same chip; and

wherein the PHY interface is designed to be physically connectable with the first type of non-volatile memory device, and to be physically connectable the second type of non-volatile memory device.

33. An apparatus comprising:

a first memory controller that corresponds with a first type of non-volatile memory device;

a second memory controller that corresponds to a second type of non-volatile memory device, wherein the second type of non-volatile memory device is different from the first type of non-volatile memory device;

an physical layer (PHY) interface; and

an interface controller coupled to the PHY interface for controlling signal transmission by the PHY interface;

wherein the interface controller is configured to control signal transmission by the PHY interface based on a manner in which pins of the PHY interface is configured by a user;

wherein both the first memory controller corresponding with the first type of non-volatile memory device and the second memory controller corresponding with the second type of non-volatile memory device are implemented on a same chip; and

wherein the PHY interface is designed to be physically connectable with the first type of non-volatile memory device, and to be physically connectable with the second type of non-volatile memory device.