Memory Processing Unit

• US 20190362787A1
• Filed: 05/22/2018
• Published: 11/28/2019
• Est. Priority Date: 05/22/2018
• Status: Active Grant

• Current Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: LU, Wei, ZIDAN, Mohammed A.
• Granted Patent: US 10,943,652 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 2207/4814 Non-logic devices, e.g. operational amplifiers
• CPC Class Codes: G06F 2207/4828 Negative resistance devices, e.g. tunnel diodes, gunn effect devices
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

An in-memory computing system for computing vector-matrix multiplications includes an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline. The in-memory computing system also includes an interface circuit electrically coupled to each bitline of the array of resistive memory devices and computes the vector-matrix multiplication between an input vector applied to a given set of wordlines and data values stored in the array. For each bitline, the interface circuit receives an output in response to the input being applied to the given wordline, compares the output to a threshold, and increments a count maintained for each bitline when the output exceeds the threshold. The count for a given bitline represents a dot-product.

Claims

1. An in-memory computing system for performing multiply-accumulate (MAC) operations and computing vector-matrix multiplications, comprising:

an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline, each resistive memory device in the array of resistive memory devices has an associated threshold voltage and is configured to store a data value therein as a resistance value; and

an interface circuit electrically coupled to each bitline of the array of resistive memory devices and cooperatively operates with the array of resistive memory devices to compute a vector-matrix multiplication between an input applied to a set of wordlines and data values stored in the array of resistive memory devices, where the interface circuit, for each bitline;

receives an output in response to the input being applied to a given word line;

compares the output to a threshold; and

increments a count maintained for each bitline when the output exceeds the threshold, such that the count for a given bitline represents the MAC operation performed between the input and conductance of the resistive memory device interconnected by the given bitline and the given wordline.

2. The in-memory computing system of claim 1 wherein the input applied to the given wordline is a voltage applied to the given wordline as a pulse, and wherein the output of each bitline is a current value.

3. The in-memory computing system of claim 2 wherein the input is a series of pulses, and wherein a total of the series of pulses represents a non-binary value.

4. The in-memory computing system of claim 1 wherein the input is applied to each wordline sequentially.

5. The in-memory computing system of claim 1 further comprising a decoder electrically coupled to each wordline, wherein the decoder is configured to apply the input to each wordline.

6. The in-memory computing system of claim 1 further comprising a plurality of comparators, wherein each comparator of the plurality of comparators is electrically coupled to a corresponding bitline, and wherein a respective comparator receives the output from the corresponding bitline and compares the output to a threshold associated with the respective comparator.

7. The in-memory computing system of claim 6 further comprising a plurality of counters, wherein each counter of the plurality of counters is electrically coupled to a corresponding comparator and, in response to the output exceeding the threshold associated with the respective comparator, incrementing a count of a respective counter.

8. The in-memory computing system of claim 1 wherein each device in the array of resistive memory devices stores at least one of a resistance value and a conductance value, and wherein at least one of the resistance value and the conductance value is an element of a potential feature represented in a column of the array of resistive memory devices.

9. The in-memory computing system of claim 1 wherein multiple resistive memory devices store multi-bit values in an identified bitline in the array of resistive memory devices.

10. The in-memory computing system of claim 1 wherein multiple resistive memory devices store multi-bit values in an identified wordline in the array of resistive memory devices.

11. The in-memory computing system of claim 1 wherein multiple arrays of resistive memory devices store multi-bit values.

12. The in-memory computing system of claim 1 wherein the interface circuit is implemented with an analog to digital converter.

13. An in-memory computing method for performing multiply-accumulate (MAC) operations and computing vector-matrix multiplications, comprising:

applying an input to an array of resistive memory devices arranged in columns and rows, wherein the array is arranged such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline, and wherein each resistive memory device in the array of resistive memory devices has an associated threshold voltage and is configured to store a data value therein as a resistance value;

computing vector-matrix multiplication between an input applied to a given set of wordlines and data values stored in the array of resistive memory devices by, for each bitline;

receiving an output in response to the input being applied to a given wordline;

comparing the output to a threshold; and

incrementing a count for each bitline when the output exceeds the threshold, such that the count of a given bitline performs MAC operation between the input and a conductance of the resistive memory device interconnected by the given bitline and the given wordline.

14. The in-memory computing method of claim 13 wherein the input applied to the given wordline is a voltage pulse, and wherein the output of each bitline is a current value.

15. The in-memory computing method of claim 14 wherein the input is a series of pulses, and wherein a total of the series of pulses represents a non-binary value.

16. The in-memory computing method of claim 13 further comprising applying the input to each wordline sequentially.

17. The in-memory computing method of claim 13 further comprising applying the input to each wordline using a decoder.

18. The in-memory computing method of claim 13 further comprising receiving the output from the given bitline at a respective comparator and comparing the output to a threshold associated with the respective comparator.

19. The in-memory computing method of claim 18 further comprising, in response to the output exceeding the threshold associated with the respective comparator, incrementing a count of a respective counter.

20. The in-memory computing method of claim 13 wherein each device in the array of resistive memory devices stores at least one of a resistance value and a conductance value, and wherein at least one of the resistance value and the conductance value is an element of a potential feature vector represented in a column of the array of resistive memory devices.