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SEMICONDUCTOR MEMORY DEVICE

  • US 20190362792A1
  • Filed: 09/17/2018
  • Published: 11/28/2019
  • Est. Priority Date: 05/28/2018
  • Status: Active Grant
First Claim
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1. A semiconductor memory device comprising:

  • a memory structural body including first and second planes each of which includes memory cells coupled to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and which are disposed along the first direction; and

    a logic structural body disposed between a substrate and the memory structural body, and including a row decoder,wherein the row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit,wherein the block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, andwherein the pass transistor circuit is disposed in an interval region between the first plane region and the second plane region.

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