AUTOMATIC DETECTION OF CHANGE IN PLL LOCKING TREND

• US 20190379525A1
• Filed: 08/23/2019
• Published: 12/12/2019
• Est. Priority Date: 04/21/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSAI, Tsung-Hsien, CHANG, Chih-Hsien
• Granted Patent: US 10,644,869 B2
• Time in Patent Office: Days
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0994 comprising an accumulator
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Claims

1. An apparatus, comprising:

a trend detector configured to determine a trend of a signal; and

a trend change detector configured to initiate a change in a mode of operation of the apparatus in response to detecting a change in the trend of the signal.

2. The apparatus of claim 1, wherein the trend comprises:

a positive trend;

a negative trend;

or

a flat trend.

3. The apparatus of claim 1, further comprising:

a clock generator configured to determine a trend clocking signal based on the reference input signal and the signal,

wherein the trend detector is configured to sample the signal based on the trend clocking signal.

4. The apparatus of claim 3, wherein the clock generator is further configured to:

provide the trend clocking signal at a first logical value in response to the signal being at a first digital value,

hold the trend clocking signal at the first logical level until the signal changes to a second digital value, and

switch the trend clocking signal from the first logical level to the second logical level in response to the signal changing to the second digital value.

5. The apparatus of claim 1, wherein the signal represents a difference between a reference input signal and an output signal of the apparatus, and wherein the apparatus comprises a phase lock loop configured to:

adjust a frequency of the output signal to be proportional to a frequency of the reference input signal in a frequency tracking mode of operation, and

adjust a phase of the output signal to match a phase of the reference input signal in a phase tracking mode of operation, and

wherein the trend change detector is further configured to switch a mode of operation of the apparatus between the frequency tracking mode of operation and the phase tracking mode of operation in response to detecting the change in the trend of the sampled signal.

6. The apparatus of claim 5, further comprising:

a phase frequency detector (PFD) configured to compare a frequency of the reference input signal and a frequency of the output signal to provide a frequency difference of the signal in the frequency tracking mode of operation and in the phase tracking mode of operation.

7. The apparatus of claim 6, further comprising:

a time-to-digital converter (TDC) configured to;

compare a phase of the reference input signal and a phase of the output signal to provide a phase difference of the signal in the phase tracking mode of operation, and

be disabled in the frequency tracking mode of operation.

8. A method for operating an apparatus, the method comprising:

detecting a change in a trend of a signal; and

initiating a change in a mode of operation of the apparatus from a frequency tracking mode of operation to a phase tracking mode of operation in response to detecting the change in the trend of the signal.

9. The method of claim 8, wherein the trend comprises:

a positive trend;

a negative trend;

or

a flat trend.

10. The method of claim 8, further comprising:

sampling the signal from the apparatus received in a frequency tracking mode of operation, the signal representing a difference between a reference input signal of the apparatus and an output signal of the apparatus;

determining a trend clocking signal based on the reference input signal and the signal, and

wherein the sampling comprises;

sampling the signal based on the trend clocking signal.

11. The method of claim 10, wherein the determining the trend clocking signal comprises:

providing the trend clocking signal at a first logical value in response to the signal being at a first digital value,

holding the trend clocking signal at the first logical level until the signal changes to a second digital value, and

switching the trend clocking signal from the first logical level to the second logical level in response to the signal changing to the second digital value.

12. The method of claim 8, further comprising:

sampling the signal from the apparatus received in a frequency tracking mode of operation, the signal representing a difference between a reference input signal of the apparatus and an output signal of the apparatus;

adjusting a frequency of the output signal to be proportional to a frequency of the reference input signal in a frequency tracking mode of operation;

adjusting a phase of the output signal to match a phase of the reference input signal in the phase tracking mode of operation; and

switching a mode of operation of a phase lock loop between the frequency tracking mode of operation and the phase tracking mode of operation in response to detecting the change in the trend of the signal.

13. The method of claim 12, wherein the adjusting the frequency of the output signal comprises:

comparing a frequency of the reference input signal and a frequency of the output signal to provide a frequency difference of the signal in the frequency tracking mode of operation and in the phase tracking mode of operation.

14. The method of claim 13, wherein the adjusting the phase of the output signal comprises:

comparing a phase of the reference input signal and a phase of the output signal to provide a phase difference of the signal in the phase tracking mode of operation.

15. An apparatus, comprising:

a clock generator configured to;

receive a signal, and

generate a clock signal based on the signal;

a trend detector configured to;

sample the signal based on the clock signal, and

determine a trend of the sampled signal; and

a trend change detector configured to;

compare the trend of the sampled signal to a previous trend of the sampled signal to detect a change in the trend of the sampled signal, and

initiate a change in a mode of operation of the apparatus in response to detecting the change in the trend of the sampled signal.

16. The apparatus claim 15, wherein the signal represents a difference between a frequency or a phase of a reference input signal of the apparatus and a frequency or a phase of an output signal of the apparatus, and the clock generator is further configured to collect a plurality of samples of the output signal and to switch logical levels of the clock signal in response to changes between the plurality of samples to generate the clock signal.

17. The apparatus claim 16, wherein the reference input signal and the output signal comprise a digital reference input signal and a digital output signal, respectively.

18. The apparatus claim 16, wherein the reference input signal represents a digital representation of a first time-varying signal having a first frequency and a first phase,

wherein the output signal represents a digital representation of a second time-varying signal having a second frequency and a second phase,

wherein the apparatus comprises a phase lock loop configured to adjust the second frequency to be proportional to the first frequency in a frequency tracking mode of operation and to change to a phase tracking mode of operation in response to the change in the mode of operation of the apparatus to adjust the second phase to be proportional to the first phase.

19. The apparatus claim 15, wherein the trend of the sampled signal comprises:

a positive trend;

a negative trend;

or

a flat trend.

20. The apparatus claim 15, wherein the apparatus further comprises:

an all-digital phase lock loop (ADPLL).